Quantum computers in this day and age are characterized by high error rates and their limited amount of qubits. This introduces errors to the execution of quantum circuits. Consequently, quantum computers currently cannot be expected to run arbitrary circuits successfully. In this context, the size of a circuit heavily influences the outcome of the execution, as large circuits are prone to errors. The size of a circuit is defined by w*d where w is its width and d its depth. Metrics can be used to judge the computational power of quantum computers and allow predictions on whether a circuit is expected to run successfully or not. In this thesis, gate-based quantum computers were benchmarked by executing randomized circuits and comparing the results to the quantum simulator’s result. Four different metrics were considered to evaluate whether the quantum computer’s result is too erroneous to consider the benchmark successful or not. After comparing the metrics and discussing possibilities as to how they can be used to evaluate benchmarks, it was decided that the histogram intersection is the most appropriate to use. Using this metric, it is possible to benchmark quantum computers with randomized circuits of different sizes, evaluate the results and use that data to find upper limits on the circuit size. The data in this thesis suggests that, for IBM’s quantum computer imbq_athens, circuits of size w*d <= 20 are expected to return acceptable results while circuits of width equal to 4 or 5 deliver acceptable results for even larger circuits (up to w*d = 40). The framework provided in this thesis is the foundation to determine the metric w*d < k*1/epsilon_eff which will be used in the automated selection of an appropriate quantum computer for a given quantum circuit.