As the overall goal this work focuses on the storage of high-speed video data, used in scientific experiments and many modern manufacturing processes. In these applications the frame rate is about 1,000 to 10,000 frames per second. These high picture rates cause extremely high bit rates, which need to be processed in a short time. One way of approaching this problem is to store the pictures in a local RAM-likememory during shooting for later processing and storage. However, the size of the memory limits the time span that can be recorded. Therefore the goal is to develope a real-time compression scheme which does not lose any data information and which makes direct recording on hard disk possible.

This diploma thesis proposes a high-level architecture design, which consists atleast of a CMOS high-speed image sensor and an FPGA which implements the compression system. The observed metrics range from amount of data, memory size and bandwidth, costs, and I/O ports to computing performance. The compression algorithm considered for a first prototype-implementation is a simple differential encoding scheme. For this scheme a mathematical model is presented, which gives answers regarding the compression gain in terms of entropy depending on changes in speed, frame rate, and size of moved area. The CMOS image sensor used is marked by noise. The different noise sources are presented and a model allowing pixel-wise creation of noise is developed. A widely used algorithm for image restoration is presented. The impact of noise and noise filter algorithm on the differential encoding system is analysed regarding the compression performance and using all the mathematical models proposed before. At the end the results and a conclusion are presented. To stimulate further research in designing a more complex compression system in the future several lossless compression systems which are presented in literature are investigated to expose the different building blocks used.