Master Thesis MSTR-2007-06

BibliographyAwan, Muhammad: Transaction Level Power and Timing Exploration of Bus Architecture.
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 6 (2007).
85 pages, english.
Abstract

kein Abstract.

Department(s)University of Stuttgart, Institute of Technical Computer Science, Embedded Systems Engineering
Superviser(s)Radetzki, Prof. Martin; Khaligh, Rauf Salimi
Entry dateMarch 2, 2020
   Publ. Computer Science