Master Thesis MSTR-2013-04

BibliographyBasak, Chiranjeeb: Design and Development of an FPGA based OFDMA Architecture for Powerline Communication.
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 4 (2013).
77 pages, english.


The communication infrastructure is an integral part of the industrial production lines. The latter faces new challenges, namely growing requirements on mobility and flexibility. In order to keep up with the pace of the ever growing requirements, the communication framework needs to be scalable and robust. The industrial production lines are operating at real-time and as such, factors like data rate, latency, real-time data processing need to be addressed when designing a robust infrastructure for an industrial environment. A general industrial communication framework consists of a number of layers, each having a defined functionality and characterized with varying reaction time, jitter and data per cycle. At the bottom layer are the field buses, which do not span all the layers and therefore does not provide a comprehensive communication solution. Address therefore needs to be given where all the levels are provided with a common platform having consistent communication solution.

Ethernet is a possible candidate to realize the various industrial requirements. With the appropriate adjustments, it can meet the real time requirements of an industrial system and at the same time can connect the different segments of the industrial communication framework thus providing a comprehensive solution. A number of protocols exist that define the usability of this physical media. One such industrial Ethernet-based protocol is the Powerlink and the aim of this thesis project is to expand the capabilities of this protocol through the usage of a different PHY level medium, the Power Line cables.

In Power Line Communication multiple numbers of end devices could constitute a production line. These devices will interact and exchange real time data over the communication entity. Thus the possibility of multiple access needs to be integrated along with the communication framework. A number of multiple access techniques such as Time Division Multiple Access (TDMA) exist and can be used to realize the aforementioned requirement. The thesis project aims to implement Orthogonal Frequency Division Multiple Access (OFDMA) in coordination with Powerline. Owing to the better spectral usage and fulfillment of the industrial requirement, OFDMA has been considered as a better candidate among the others for the implementation and integration with Powerline.

The project is realized over Altera FPGA development boards. The aim is to develop an OFDMA system that can be used to connect multiple numbers of end devices. The end devices are considered to be machine drives operating at real time. For the implementation, the drives are modeled as FPGA boards. The system is to be synthesized on the hardware and then tested for validation and verification. Initially the multiple access is to be realized by static allocation of subcarriers. The end users are to be pre-allocated with a fixed number of data subcarriers. The target is to allocate half the total number of subcarriers to the Master drive and dividing the rest half carefully to the other end users. The users are to be identified by the subcarrier identity thus allowing for a wider data.

Once completed, the system can be extended to check the feasibility of dynamic carrier allocation.

Department(s)University of Stuttgart, Institute of Parallel and Distributed Systems, Parallel Systems
Superviser(s)Simon, Prof. Sven; Klaiber, Michael
Entry dateMarch 26, 2020
   Publ. Computer Science