Abstract:

Peripheral Component Interconnect (PCI) has remained an integral part of the computer’s architecture for connecting sound, video and network cards to the motherboard. However, it suffers with bandwidth limitations as the processors, video, sound and network cards have become very fast and powerful. Thus, it is unable to handle many devices at the same time. This master thesis is a step towards replacing the old parallel PCI bus interface with recent serial architecture of PCI Express. PCI Express (PCIe) is the new generation from the PCI Input/Output (I/O) bus technology from the PCI Special Interest Group (SIG) which aims at supporting the ever increasing bandwidth requirements of today’s advanced I/O devices. It follows a serial based architecture unlike its predecessors and offers a bandwidth up to a maximum of 31.51GB/s with future PCIe version 4.0. These new high-performance specs may not see broad adoption in embedded applications for a while, but data-centric demands continue to drive throughput, power and cost requirements to high levels. This thesis aims at analysing and evaluating the performance of PCI Express version 2.0 for high speed DMA accesses and the latency effects of random memory accesses that may take place during the DMA operations. The results of this thesis creates a basis for optimization for new innovative embedded applications using FPGAs, image processing in High Definition video and signal processing using PCIe. The high-end medical and military image/video processing are seen as future potential market segments.