The continuously shrinking technology has made it possible for designers to incorporate more functionality with better performance at a much higher density in Integrated Circuits( ICs). Fast and accurate timing simulation of such large circuit designs using ever more complex transistor models has become a challenging problem. In modern circuits, the gate delay is severely affected by process variations, environmental variations and cross talk. Moreover, technology scaling has also resulted in significant increase in interconnect parasitics (including resistors and capacitors) which can dramatically reduce the performance of a circuit. For the circuit design validation and delay test evaluation, the industry has long relied on fast gate-level timing simulators like ModelSim to validate the designs. However, with continued scaling and steadily increasing circuit performance requirements, gate level simulators can no longer provide acceptable simulation accuracy. On the other hand, circuit level SPICE simulation provides acceptable accuracy but at a very large computational cost. To provide a suitable trade-off between the accuracy of the SPICE simulation and the speed of the gate level simulation, this thesis proposes a realistic gate model which can be used for the fast and accurate timing simulation of circuits to analyze their timing behaviour. In this thesis, a heterogeneous gate model that combines a simple gate model like Non- Linear Delay Model (NLDMs) and an advanced current source model (CSM) using a classifier is proposed. The simple gate model allows fast timing simulation and gives acceptable accuracy in many cases while the advanced gate model always provides more accurate and reliable results, but at a much higher computational cost. The classifier is designed to choose the advanced gate model depending on special cases (eg, multiple input switching) where the simple gate model gives inappropriate results. This heterogeneous gate model is further applied to develop a circuit simulator that enables fast and accurate post-layout and delay fault simulation.