Today, defect localization and fault identification problems are addressed by many diagnostic techniques each of which give focus on locating the defects and modeling their logic behaviors. In most of these techniques, defects are assumed to be localized, that is, circuit elements like transistors, gates or interconnects affected by a defect are confined to a restricted region in IC layout. This fact at first glance necessitates utilization of layout information in order to locate regions identified as potentially faulty. By mapping diagnosis results into layout and rapid navigating through these suspected regions, the defect mechanism in a faulty chip can be understood more in detail.

Quick and precise layout exploration therefore becomes a crucial issue but also a potential problem as the complexity of IC increases. The fact that a huge IC layout may contain billions of geometry elements in space makes navigation performance a big bottleneck. To avoid this, layout navigation problem should be supported with efficient geometrical algorithms which help quick search of desired layout regions. In the presence of these algorithms, interactive localization can also be achieved by mirroring defect locations in different abstraction levels of IC design.

The objective of this thesis work is to help realize such a scheme while providing bidirectional circuit referencing between layout and gate netlist descriptions. By this means, circuit elements which lie in the physical neighborhood of suspected defect locations in layout will be mapped to the corresponding circuit elements in netlist and vice versa.