This thesis is part of a project in which a high speed camera is developed. Subject of this work is the interconnection of an image sensor LUPA-3000 and a FPGA. The FPGA is connected to the multi channel LVDS data interface and handles the calibration of the individual channels. The LVDS receiver interface can handle asynchronous data signals and synchronizes them for subsequent processing. This complex LVDS receiver design is discussed and its functionality explained in detail.For testing, a VHDL design was developed including an asynchronous LVDS transmitter that transfers data to the receiver component through wires which interconnect the FPGA IOs. After simulating the entire design it was tested in practice on a FPGA evaluation board. This communication system was verified utilizing a ChipScope logic analyzer. The interface design which is connected to the image sensor includes the receiver component as well as an unit that provides an easy to use configuration interface for programming the image sensor. Besides, the exposure control is realized within the VHDL design. To evaluate the hardware design, that is connected to the image sensor, a SystemC testbench was developed, that includes a software model of the LUPA-3000 image sensor to verify the functionality of the overall design.