Although vast research has been conducted by the processor industry the most recent processors are still based on the traditional Von Neumann architecture which suers from performance and power issues. In order to investigate an alternative approach a novel coprocessor architecture has been developed at IBM Research in Zurich which addresses some of the issues of the former approach. The architecture, with multiple dual threaded cores is based on the concept of programmable state machine technology. In the following thesis, we show how the novel coprocessor architecture will be evaluated and any improvements, which would bene t the architecture, will be proposed. Throughout this thesis the evaluation of the architecture is performed using cryptographic algorithms which were chosen for this purpose. In order to map the algorithms on our architecture we propose a new programming methodology. The proposed methodology is architecture independent and can be easily adapted to any other programmable state machine based architectures. SHA-1 from the group of authentication algorithms and AES from the group of encryption algorithms are chosen as test vehicles. However, the principles used in this work are applicable to other cryptographic algorithms. An ecient mapping of both SHA-1 and AES algorithms was enabled by refactoring the basic structure of the algorithm. The proposed implementations achieved a throughput of 720 Mbps and 80 Mbps for SHA-1 and AES algorithms respectively. During the thesis, we proposed some improvements to the architecture. The proposed changes were incorporated by modifying the VHDL source. With these proposed changes the throughput of the SHA-1 algorithm is increased by 70% and the AES algorithm is increased by 150%. The results of the proposed system are compared with the related works in recon gurable hardware and also on a processor.