Master Thesis MSTR-3097

BibliographyBoktor, Andrew: Development of an Error Detection and Recovery Technique for a SPARC V8 Processor in FPGA Technology.
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 3097 (2011).
43 pages, english.
CR-SchemaB.8.1 (Reliability, Testing, and Fault-Tolerance)
C.4 (Performance of Systems)
C.5.3 (Microcomputers)
C.1.3 (Processor Architectures, Other Architecture Styles)
Abstract

Field-Programmable Gate Arrays (FPGAs) found widespread use in many areas of applications, including safety and mission-critical systems. More and more manufacturers are choosing to implement designs on FPGAs. However, SRAM-based FPGAs are proven to be much more prone to Single Event Upsets (SEUs) compared to traditional Application-Specific Integrated Circuit (ASIC) designs. Moreover, SEU affects FPGAs in more severe ways compared to ASIC. Techniques to provide fault-tolerance for SRAM-based FPGAs become essential to maintain their advantages over other technologies.

This thesis presents a fault-tolerance technique for pipeline architectures in FPGA technology. It provides fault-tolerance against SEUs in the design and is able to detect faults in the FPGA configuration. It also proposes an additional mechanism that detects all SEUs independent of their location. Pipeline operation can be resumed with known techniques of partial reconfiguration. Both designs occupy a much smaller area compared to known techniques such as TMR in combination with Scrubbing. They introduce no additional time penalty in case of fault-free operation. Fault injection and simulation were used to validate the design and calculate the fault coverage.

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Department(s)University of Stuttgart, Institute of Technical Computer Science, Computer Architecture
Superviser(s)Baranowski, Rafal
Entry dateJuly 14, 2011
   Publ. Computer Science