The watershed algorithm is a commonly used method of solving the image segmentation problem. However, of the many variants of the watershed algorithm not all are equally well suited for hardware implementation. Different algorithms are studied and the watershed algorithm based on connected components is selected for the implementation, as it exhibits least computational complexity, good segmentation quality and can be implemented in the FPGA. It has simplified memory access compared to all other watershed based image segmentation algorithms. This thesis proposes a new hardware implementation of the selected watershed algorithm. The main aim of the thesis is to implement image segmentation algorithm in a FPGA which requires minimum hardware resources, low execution time and is suitable for use in real time applications.

A pipelined architecture of algorithm is designed, implemented in VHDL and synthesized for Xilinx Virtex-4 FPGA. In the implementation, image is loaded to external memory and algorithm is repeatedly applied to the image. To overcome the problem of over-segmentation, pre-processing step is used before the segmentation and implemented in the pipelined architecture. The pipelined architecture of pre-processing stage can be operated at up to 228 MHz. The computation time for a 512 x 512 image is about 35 to 45 ms using one pipelined segmentation unit. A proposal of parallel architecture is discussed which uses multiple segmentation units and is fast enough for the real time applications. The implemented and proposed architectures are excellent candidates to use for different applications where high speed performance is needed.