Bibliograph.
Daten | Buntoro, David Prasetyo: Modeling of Design-for-test infrastructure in complex Systems-on-chips.
Universität Stuttgart, Fakultät Informatik, Elektrotechnik und Informationstechnik, Masterarbeit Nr. 3304 (2012).
35 Seiten, englisch.
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| CR-Klassif. | B.5.1 (Register-Transfer-Level Implementation, Design)
B.5.3 (Reliability and Testing)
C.5.3 (Microcomputers)
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| Kurzfassung | Every integrated circuit contains a piece of design-for-test (DFT) infra- structure in order to guarantee the chip quality after manufacture. The DFT resources are employed only once in the fab and are usually not available during regular system operation.
In order to assess the hardware integrity of a chip over its complete life- cycle, it is promising to reuse the DFT infrastructure as part of system- level test.
In this thesis, the provided system, a Tricore processor from Infineon, must be partitioned and modified in order to enable the autonomous structural test of every component of the system in the field without expensive external tester.
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Volltext und
andere Links | PDF (1077775 Bytes)
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| Abteilung(en) | Universität Stuttgart, Institut für Technische Informatik, Rechnerarchitektur
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| Betreuer | M.Sc. Alejandro Cook |
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| Eingabedatum | 26. September 2012 |
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