| Bibliography | Ma, Sijia: Analysis of Hierarchical Design Methodology for FPGA Hardware Design.
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 3524 (2013).
78 pages, english.
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| CR-Schema | B.5.1 (Register-Transfer-Level Implementation, Design)
B.5.2 (Register-Transfer-Level Implementation, Design Aids)
B.5.3 (Reliability and Testing)
B.6.1 (Logic Design, Design Styles)
B.6.3 (Logic Design, Design Aids)
B.8.1 (Reliability, Testing, and Fault-Tolerance)
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| Abstract | wurde nicht veröffentlicht
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| Department(s) | University of Stuttgart, Institute of Parallel and Distributed Systems, Parallel Systems
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| Superviser(s) | Klaiber, Michael |
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| Entry date | March 10, 2014 |
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