Master Thesis MSTR-3524

BibliographyMa, Sijia: Analysis of Hierarchical Design Methodology for FPGA Hardware Design.
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 3524 (2013).
78 pages, english.
CR-SchemaB.5.1 (Register-Transfer-Level Implementation, Design)
B.5.2 (Register-Transfer-Level Implementation, Design Aids)
B.5.3 (Reliability and Testing)
B.6.1 (Logic Design, Design Styles)
B.6.3 (Logic Design, Design Aids)
B.8.1 (Reliability, Testing, and Fault-Tolerance)

wurde nicht veröffentlicht

Department(s)University of Stuttgart, Institute of Parallel and Distributed Systems, Parallel Systems
Superviser(s)Klaiber, Michael
Entry dateMarch 10, 2014
   Publ. Computer Science