Master Thesis MSTR-3525

BibliographyDessouky, Ghada: Design and Implementation of Adaptive On-Chip Memory Management for FPGA- based Image Processing Architectures.
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 3525 (2014).
117 pages, english.
CR-SchemaB.4.3 (Interconnections (Subsystems))
B.5.1 (Register-Transfer-Level Implementation, Design)
B.5.2 (Register-Transfer-Level Implementation, Design Aids)
B.6.1 (Logic Design, Design Styles)
B.6.3 (Logic Design, Design Aids)
B.7.1 (Integrated Circuits, Types and Design Styles)
B.7.2 (Integrated Circuits, Design Aids)
C.1.2 (Multiple Data Stream Architectures (Multiprocessors))
C.1.3 (Processor Architectures, Other Architecture Styles)
C.3 (Special-Purpose and Application-Based Systems)

wurde nicht veröffentlicht

Department(s)University of Stuttgart, Institute of Parallel and Distributed Systems, Parallel Systems
Superviser(s)Klaiber, Michael
Entry dateAugust 11, 2014
   Publ. Computer Science