In todays VLSI chip manufacturing processes variations occur, that may manifest as delay defects and affect the timing behaviour of the circuit. In general, these delay faults only occur under at-speed test conditions and it requires special effort to simulate them. Since fault simulation is inherently parallelizable, NVIDIAs Compute Unified Device Architecture (CUDA) is used for utilizing general purpose graphics processing units (GPGPUs) in order to exploit available parallelism. The goal of this study thesis was the implementation of a delay fault simulator to simulate the behaviour of small delay faults on CUDA devices and its integration into a diagnosis framework for application of the Partially Overlapping Impact couNTER (POINTER) algorithm. A series of experiments was performed to observe the diagnosability of the delay faults.