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- Ahmed, Ibrahim: Reliable Routing Table Reconfiguration for On-chip Network Switches, Master Thesis No. 3664, 2014.
- Awan, Muhammad: Transaction Level Power and Timing Exploration of Bus Architecture, Master Thesis No. 6, 2007.
- Batzolis, Nikolaos: Design of a Fault Tolerant End-to-End Flow Control Protocol for Networks on Chip, Master Thesis No. 9, 2011.
- Bruni, Thomas: A Formalized Approach to Transaction Level Modeling, Master Thesis No. 12, 2007.
- Eissa, Karim: Modeling of a multi-core microblaze system at RTL and TLM abstraction levels in systemC, Master Thesis No. 3, 2013.
- Hartmann, Julien: Mehrdimensionale, automatisierte Ermittlung von Antriebsstrang Software-Varianten für Release-Konformität, Master Thesis No. 17, 2023.
- Hasan, Nouman Naim: Optimization of Microprocessor-based Systems for Smart MEMS, Master Thesis No. 4, 2014.
- Khaligh, Rauf Salimi: Transcaction Simulation of ARM Based Platforms, Master Thesis No. 3, 2006.
- Saurabh, Saket: Reflective Learning with Prompts, Master Thesis No. 16, 2023.
- Shah, Dhaval A: A Dual Core Sytsem for IoT Sensor Nodes, Master Thesis No. 5, 2014.
- Zixuan, Cheng: Transaction-Level Instruction Set Simulator of megaAVR Micro-controller, Master Thesis No. 6, 2012.
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