Dorsch, Rainer; Wunderlich, Hans-Joachim: Reusing Scan Chains for Test Pattern Decompression. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 18(2), Springer Netherlands, 2002.
Girard, Patrick; Landrault, Christian; Pravossoudovitch, Serge; Virazel, Arnaud; Wunderlich, Hans-Joachim: High Defect Coverage with Low Power Test Sequences in a BIST Environment. In: IEEE Design and Test of Computers. Vol. 19(5), IEEE Computer Society, 2002.
Hellebrand, Sybille; Wunderlich, Hans-Joachim; Ivaniuk, Alexander A.; Klimets, Yuri V.; Yarmolik, Vyacheslav N.: Efficient On- and Off-Line Testing of Embedded DRAMs. In: IEEE Transaction on Computers. Vol. 51(7), IEEE Computer Society, 2002.
Liang, Hua-Guo; Hellebrand, Sybille; Wunderlich, Hans-Joachim: Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 18(2), Springer Netherlands, 2002.

Hellebrand, Sybille; Liang, Hua-Guo; Wunderlich, Hans-Joachim: A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 17(3/4), Springer Netherlands, 2001.
Kiefer, Gundolf; Vranken, Harald; Marinessen, Erik Jan; Wunderlich, Hans-Joachim: Application of deterministic logic BIST on industrial circuits. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 17(3), Springer Netherlands, 2001.

Gerstendoerfer, Stefan; Wunderlich, Hans-Joachim: Minimized Power Consumption for Scan-Based BIST. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 16(3), Springer Netherlands, 2000.
Kiefer, Gundolf; Wunderlich, Hans-Joachim: Deterministic BIST with Partial Scan. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 16(3), Springer Netherlands, 2000.

Kiefer, Gundolf; Wunderlich, Hans-Joachim: Deterministic BIST with Multiple Scan Chains. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 14(1-2), Springer Netherlands, 1999.

Hellebrand, Sybille; Wunderlich, Hans-Joachim; Hertwig, Andre: Synthesizing fast, online-testable control units. In: IEEE Design & Test of Computers,. Vol. 15(4), IEEE Computer Society, 1998.
Hellebrand, Sybille; Wunderlich, Hans-Joachim; Hertwig, Andre: Mixed-Mode BIST Using Embedded Processors. In: Journal of Electronic Testing - Theory and Applications (JETTA). Vol. 12(1-2), Springer Netherlands, 1998.
Stroele, Albrecht P.; Wunderlich, Hans-Joachim: Hardware-Optimal Test Register Insertion. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 17(6), IEEE Circuits and Systems Society, 1998.
Wunderlich, Hans-Joachim: BIST for Systems-on-a-Chip. In: INTEGRATION, The VLSI Journal. Vol. 26(1-2), Elsevier Science B.V, 1998.