@inproceedings {INPROC-1997-32,
    author = {Andre Hertwig and Hans-Joachim Wunderlich},
    title = {{Fast Controllers for Data Dominated Applications}},
    booktitle = {Proceedings of the European Design \& Test Conference (ED\&TC), Paris, France, March 1997},
    publisher = {Institute of Electrical and Electronics Engineers},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
    pages = {84--89},
    type = {Konferenz-Beitrag},
    month = {M{\"a}rz},
    year = {1997},
    isbn = {0-8186-7786-4},
    isbn = {ISSN 1066-1409},
    doi = {10.1109/EDTC.1997.582337},
    keywords = {FSM synthesis, performance driven synthesis; synthesis of testable controllers},
    language = {Englisch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
    abstract = {A target structure for implementing fast edge-triggered control units is
      presented. In many cases, the proposed controller is faster than a one-hot
      encoded structure as its correct timing does not require master-slave
      flip-flops even in the presence of unpredictable clocking skews. A synthesis
      procedure is proposed which leads to a performance improvement of 40\% on
      average for the standard benchmark set whereas the additional area is less than
      25\% compared with conventional finite state machine (FSM) synthesis. The
      proposed approach is compatible with the state-of-the-art methods for FSM
      decomposition, state encoding and logic synthesis.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1997-32&engl=0}
 }

@inproceedings {INPROC-1997-31,
    author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
    title = {{Using BIST Conitrol for Pattern Generation}},
    booktitle = {Proc. of the 28th IEEE International Test Conference (ITC), Washington, DC, November 1997},
    publisher = {International Test Conference},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
    pages = {347--355},
    type = {Konferenz-Beitrag},
    month = {November},
    year = {1997},
    isbn = {0-7803-4209-7},
    issn = {1089-3539},
    doi = {10.1109/TEST.1997.639636},
    keywords = {deterministic BIST; scan-based BIST},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
    abstract = {A deterministic BIST scheme is presented which requires less hardware overhead
      than pseudo-random BIST but obtains better or even complete fault coverage at
      the same time. It takes advantage of the fact that any autonomous BIST scheme
      needs a BIST control unit for indicating the completion of the self-test at
      least.
      
      Hence, pattern counters and bit counters are always available, and they provide
      information to be used for deterministic pattern generation by some additional
      circuitry. This paper presents a systematic way for synthesizing a pattern
      generator which needs less area than a 32-bit LFSR for random pattern
      generation for all the benchmark circuits.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1997-31&engl=0}
 }