@inproceedings {INPROC-1998-43,
author = {Vyacheslav N. Yarmolik and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs}},
booktitle = {Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE), Paris, France,February 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {173--179},
type = {Konferenz-Beitrag},
month = {Februar},
year = {1998},
isbn = {0-8 186-8359-7},
isbn = {},
doi = {10.1109/DATE.1998.655853},
keywords = {built-in self test; data compression; integrated circuit testing; random-access storage},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {After write operations, BIST schemes for RAMs relying on signature analysis
must compress the entire memory contents to update the reference signature.
This paper introduces a new scheme for output data compression which avoids
this overhead while retaining the benefits of signature analysis. The proposed
technique is based on a new memory characteristic derived as the modulo-2 sum
of all addresses pointing to non-zero cells. This characteristic can be
adjusted concurrently with write operations by simple EXOR-operations on the
initial characteristic and on the addresses affected by the change.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-43&engl=0}
}
@inproceedings {INPROC-1998-42,
author = {Andre Hertwig and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Fast Self-Recovering Controllers}},
booktitle = {Proceedings of the 16th IEEE VLSI Test Symposium (VTS), Monterey, CA, April 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {296--302},
type = {Konferenz-Beitrag},
month = {April},
year = {1998},
isbn = {0-8 186-8436-4},
issn = {1093-0167},
doi = {10.1109/VTEST.1998.670883},
keywords = {FSM synthesis; fault-tolerance; checkpointing; performance-driven synthesis},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A fast fault-tolerant controller structure is presented, which is capable of
recovering from transient faults by performing a rollback operation in
hardware.
The proposed fault-tolerant controller structure utilizes the rollback hardware
also for system mode and this way achieves performance improvements of more
than 50\% compared to controller structures made fault-tolerant by conventional
techniques, while the hardware overhead is often negligible. The proposed
approach is compatible with state-of-the-art methods for FSM decomposition,
state encoding and logic synthesis.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-42&engl=0}
}
@inproceedings {INPROC-1998-41,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Accumulator Based Deterministic BIST}},
booktitle = {Proceedings of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {412--421},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {1998},
isbn = {0-7803-5092-8},
issn = {1089-3539},
doi = {10.1109/TEST.1998.743181},
keywords = {BIST; hardware pattern generator; embedded cores},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Most built-in self test (BIST) solutions require specialized test pattern
generation hardware which may introduce significant area overhead and
performance degradation. Recently, some authors proposed test pattern
generation on chip by means of functional units also used in system mode like
adders or multipliers. These schemes generate pseudo-random or
pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under
test contains random pattern resistant faults a deterministic test pattern
generator is necessary to obtain complete fault coverage.
In this paper it is shown that a deterministic test set can be encoded as
initial values of an accumulator based structure, and all testable faults can
be detected within a given test length by carefully selecting the seeds of the
accumulator. A ROM is added for storing the seeds, and the control logic of the
accumulator is modified. In most cases the size of the ROM is less than the
size required by traditional LFSR-based reseeding approaches.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-41&engl=0}
}
@inproceedings {INPROC-1998-40,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Multiple Scan Chains}},
booktitle = {Proceedings of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {1057--1064},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {1998},
isbn = {0-7803-5092-8},
issn = {1089-3539},
doi = {10.1109/TEST.1998.743304},
keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented.
A procedure is described for synthesizing a pattern generator which stimulates
all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach
while better or even complete fault coverage is obtained at the same time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-40&engl=0}
}
@inproceedings {INPROC-1998-39,
author = {Vyacheslav N. Yarmolik and Yuri Klimets and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{New Transparent RAM BIST Based on Self-Adjusting Output Data Compression}},
booktitle = {Proceedings of Design \& Diagnostics of Electronic Circuits \& Systems (DDECS), Szczyrk, Poland, September 1998},
address = {Gliwice},
publisher = {Silesian Techn. Univ. Press},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {27--33},
type = {Konferenz-Beitrag},
month = {September},
year = {1998},
isbn = {83-90840-96-0},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The new memory transparent BIST technique is proposed in this paper. It has
more higher fault coverage compare to classical transparent technique. Also
this technique decreases the test complexity up to 50\% for the most of march
tests.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-39&engl=0}
}
@inproceedings {INPROC-1998-38,
author = {Madhavi Karkal and Nur A. Touba and Hans-Joachim Wunderlich},
title = {{Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST}},
booktitle = {Proceedings of the 7th Asian Test Symposium (ATS), Singapore, December 2-4, 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {492--499},
type = {Konferenz-Beitrag},
month = {Dezember},
year = {1998},
isbn = {0-8 186-8277-9},
issn = {1081-7735},
doi = {10.1109/ATS.1998.741662},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In mixed-mode BIST, deterministic test patterns are generated with on-chip
hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed
by the pseudo-random patterns. While previous work in mixed-mode BIST has
focussed on developing hardware schemes for more efficiently encoding a given
set of deterministic patterns (generated by a conventional ATPG procedure), the
approach taken in this paper is to improve the encoding efficiency (and hence
reduce hardware overhead) by specially selecting a set of deterministic
patterns for the r.p.r. faults that can be efficiently encoded. A special ATPG
procedure is described for finding test patterns for the r.p.r. faults that are
correlated (have the same logic value) in many bit positions. Such test
patterns can be efficiently encoded with one of the many ``bit-fixing'' schemes
that have been described in the literature. Results are shown for different
bit-fixing schemes which indicate dramatic reductions in BIST overhead can be
achieved by using the proposed ATPG procedure to select which test patterns to
encode.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-38&engl=0}
}
@article {ART-1998-15,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Andre Hertwig},
title = {{Mixed-Mode BIST Using Embedded Processors}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {12},
number = {1-2},
pages = {127--138},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {1998},
issn = {0923-8174},
doi = {10.1023/A:1008294125692},
keywords = {BIST; random pattern testing; deterministic BIST; embedded systems},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In complex systems, embedded processors may be used to run software for test
pattern generation and response evaluation. For system components which are not
completely random pattern testable, the test programs have to generate
deterministic patterns after random testing. Usually the random test part of
the program requires long run times whereas the part for deterministic testing
has high memory requirements.
In this paper it is shown that an appropriate selection of the random pattern
test method can significantly reduce the memory requirements of the
deterministic part. A new, highly efficient scheme for software-based random
pattern testing is proposed, and it is shown how to extend the scheme for
deterministic test pattern generation. The entire test scheme may also be used
for implementing a scan based BIST in hardware.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-15&engl=0}
}
@article {ART-1998-14,
author = {Albrecht P. Stroele and Hans-Joachim Wunderlich},
title = {{Hardware-Optimal Test Register Insertion}},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
publisher = {IEEE Circuits and Systems Society},
volume = {17},
number = {6},
pages = {531--539},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {1998},
issn = {0278-0070},
doi = {10.1109/43.703833},
keywords = {BILBO; built-in self-test; CBILBO; test register insertion},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Implementing a built-in self-test by a ``test per clock'' scheme offers
advantages concerning fault coverage, detection of delay faults and test
application time. Such a scheme is implemented by test registers, for instance
BILBOs or CBILBOs, which are inserted into the circuit structure at appropriate
places. An algorithm is presented which is able to find the cost optimal
placement of test registers for nearly all the ISCAS'89 sequential benchmark
circuits, and a suboptimal solution with slightly higher costs is obtained for
all the circuits within a few minutes of computing time. The algorithm can also
be applied to the Minimum Feedback Vertex Set problem in partial scan desing,
and an optimal solution is found for all the benchmark circuits.
The proveably optimal solutions for the benchmark circuits mainly use CBILBOs
which can simultaneously generate test patterns and compact test responses.
Hence, test scheduling is not required, test control is simplified, and test
application time is reduced.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-14&engl=0}
}
@article {ART-1998-13,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Andre Hertwig},
title = {{Synthesizing fast, online-testable control units}},
journal = {IEEE Design \& Test of Computers,},
publisher = {IEEE Computer Society},
volume = {15},
number = {4},
pages = {36--41},
type = {Artikel in Zeitschrift},
month = {Oktober},
year = {1998},
issn = {0740-7475},
doi = {10.1109/54.735925},
keywords = {error detection; finite state machines; logic testing},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The authors present the self-checking bypass pipeline, an online-testable
controller structure for data-dominated applications. For most circuits in a
standard benchmark set, this structure leads to a performance improvement of
more than 30\% with an area overhead less than 15\% that of conventional
online-testable finite-state machines},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-13&engl=0}
}
@article {ART-1998-12,
author = {Hans-Joachim Wunderlich},
title = {{BIST for Systems-on-a-Chip}},
journal = {INTEGRATION, The VLSI Journal},
publisher = {Elsevier Science B.V},
volume = {26},
number = {1-2},
pages = {55--78},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {1998},
issn = {0167-9260},
doi = {10.1016/S0167-9260(98)00021-2},
keywords = {BIST; Systems-on-chip; Deterministic BIST; Functional BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An increasing part of microelectronic systems is implemented on the basis of
predesigned and preverified modules, so-called cores, which are reused in many
instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many
other functions, and built-in self-test ist the appropriate method for testing
complex systems composed of different cores In this paper, we overview BIST
methods for different types of cores and present advanced BIST solutions.
Special emphasis is put on deterministic BIST methods as they do not require
any modifications of the core under test and help to protect intellectual
property (IP).},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-12&engl=0}
}
@book {BOOK-1998-01,
author = {Kerstin Schneider (Hrsg.) and Hiltrud Betz and Cora Burger and Volker Claus and Waltraud Schweikhardt},
title = {{Die Informatik AG - Telekooperation.}},
address = {Stuttgart},
publisher = {B.G. Teubner-Verlag},
pages = {158},
type = {Buch},
month = {Januar},
year = {1998},
isbn = {3-519-12194-8},
keywords = {Studieninformation; Frauenf{\"o}rderung; gender; computer science},
language = {Deutsch},
cr-category = {K.3 Computers and Education},
ee = {http://www.informatik.uni-stuttgart.de/fakultaet/frauen/frauen.html,
http://medoc.informatik.uni-stuttgart.de/~medoc/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Parallele und Verteilte H{\"o}chstleistungsrechner, Anwendersoftware (Prof. Reuter);
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Formale Konzepte;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Programmiersprachen und {\"U}bersetzerbau;
Universit{\"a}t Stuttgart, Institut f{\"u}r Parallele und Verteilte H{\"o}chstleistungsrechner, Verteilte Systeme;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Visualisierung und Interaktive Systeme},
abstract = {(not available)},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=BOOK-1998-01&engl=0}
}