@inproceedings {INPROC-1999-53,
author = {Vyacheslav N. Yarmolik and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Symmetric Transparent BIST for RAMs}},
booktitle = {Proceedings of the 2nd Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 9-12, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {702--708},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {1999},
isbn = {0-7695-0078-1},
doi = {10.1109/DATE.1999.761206},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper introduces the new concept of symmetric transparent BIST for RAMs.
This concept allows to skip the signature prediction phase of conventional
transparent BIST approaches and therefore yields a significant reduction of
test time. The hardware cost and the fault coverage of the new scheme remain
comparable to that of a traditional transparent BIST scheme. In many cases,
experimental studies even show a higher fault coverage obtained in shorter test
time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-53&engl=0}
}
@inproceedings {INPROC-1999-52,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Alexander Ivaniuk and Yuri Klimets and Vyacheslav N. Yarmolik},
title = {{Error Detecting Refreshment for Embedded DRAMs}},
booktitle = {Proceedings of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 25-29, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {384--390},
type = {Konferenz-Beitrag},
month = {April},
year = {1999},
isbn = {0-7695-0146-X},
issn = {1093-0167},
doi = {10.1109/VTEST.1999.766693},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents a new technique for on-line consistency checking of
embedded DRAMs. The basic idea is to use the refresh cycle for concurrently
computing a test characteristic of the memory contents and compare it to a
precomputed reference characteristic. Experiments show that the proposed
technique significantly reduces the time between the occurrence of an error and
its detection (error detection latency). It also achieves a very high error
coverage at low hardware costs. Therefore it perfectly complements standard
on-line checking approaches relying on error detecting codes, where the
detection of certain types of errors is guaranteed, but only during READ
operations accessing the erroneous data.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-52&engl=0}
}
@inproceedings {INPROC-1999-51,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Partial Scan}},
booktitle = {Proceedings of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {110--117},
type = {Konferenz-Beitrag},
month = {Mai},
year = {1999},
isbn = {0-7695-0390-X},
doi = {10.1109/ETW.1999.804415},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An efficient deterministic BIST scheme based on partial scan chains together
with a scan selection algorithm tailored for BIST is presented. The algorithm
determines a minimum number of flipflops to be scannable so that the remaining
circuit has a pipeline-like structure. Experiments show that scanning less
flipflops may even decrease the hardware overhead for the on-chip pattern
generator besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-51&engl=0}
}
@inproceedings {INPROC-1999-50,
author = {Vyacheslav N. Yarmolik and I.V. Bykov and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms}},
booktitle = {Proceedings of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999},
address = {Berlin / Heidelberg},
publisher = {Springer},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {339--350},
type = {Konferenz-Beitrag},
month = {September},
year = {1999},
isbn = {978-3-540-66483-3},
isbn = {ISSN 0302-9743},
doi = {10.1007/3-540-48254-7_23},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a new approach to transparent BIST for word-oriented RAMs
which is based on the transformation of March transparent test algorithms to
the symmetric versions. This approach allows to skip the signature prediction
phase inherent to conventional transparent memory testing and therefore to
significantly reduce test time. The hardware overhead and fault coverage of the
new BIST scheme are comparable to the conventional transparent BIST structures.
Experimental results show that in many cases the proposed test techniques
achieve a higher fault coverage in shorter test time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-50&engl=0}
}
@inproceedings {INPROC-1999-49,
author = {Stefan Gerstendoerfer and Hans-Joachim Wunderlich},
title = {{Minimized Power Consumption for Scan-Based BIST}},
booktitle = {Proceedings of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {77--84},
type = {Konferenz-Beitrag},
month = {September},
year = {1999},
isbn = {0-7803-5753-1},
issn = {1089-3539},
doi = {10.1109/TEST.1999.805616},
keywords = {BIST; Low Power; Power consumption},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Power consumption of digital systems may increase significantly during testing.
In this paper, systems equipped with a scan-based built-in self-test like the
STUMPS architecture are analyzed, the modules and modes with the highest power
consumption are identified, and design modifications to reduce power
consumption are proposed. The design modifications include some gating logic
for masking the scan path activity during shifting, and the synthesis of
additional logic for suppressing random patterns which do not contribute to
increase the fault coverage. These design changes reduce power consumption
during BIST by several orders of magnitude, at very low cost in terms of area
and performance.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-49&engl=0}
}
@article {ART-1999-10,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Multiple Scan Chains}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {14},
number = {1-2},
pages = {85--93},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {1999},
issn = {0923-8174},
doi = {10.1023/A:1008353423305},
keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented.
A procedure is described for synthesizing a pattern generator which stimulates
all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach
while better or even complete fault coverage is obtained at the same time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1999-10&engl=0}
}