@inproceedings {INPROC-2000-46,
author = {Silvia Cataldo and Silvia Chiusano and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{Optimal Hardware Pattern Generation for Functional BIST}},
booktitle = {Proceedings of the 3rd Conference on Design and Test in Europe (DATE), Paris, France, March 27-30, 2000},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {292--297},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2000},
isbn = {0-7695-0537-6},
issn = {1530-1591},
doi = {10.1109/DATE.2000.840286},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Functional BIST is a promising solution for self-testing complex digital
systems at reduced costs in terms of area and performance degradation. The
present paper addresses the computation of optimal seeds for an arbitrary
sequential module to be used as hardware test pattern generator. Up to now,
only linear feedback shift registers and accumulator based structures have been
used for deterministic test pattern generation by reseeding. In this paper, a
method is proposed which can be applied to general finite state machines.
Nevertheless the method is absolutely general, for sake of comparison with
previous approaches, in this paper an accumulator based unit is assumed as
pattern generator module. Experiments prove the effectiveness of the approach
which outperforms previous results for accumulators, in terms of test size and
test time, without sacrifying the fault detection capability.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-46&engl=0}
}
@inproceedings {INPROC-2000-45,
author = {Gundolf Kiefer and Harald Vranken and Erik Jan Marinessen and Hans-Joachim Wunderlich},
title = {{Application of Deterministic Logic BIST on Industrial Circuits}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 200},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {105--114},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894197},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {We present the application of a deterministic logic BIST scheme on
state-of-the-art industrial circuits. Experimental results show that complete
fault coverage can be achieved for industrial circuits up to 100K gates with
10,000 test patterns, at a total area cost for BIST hardware of typically
5\%-15\%. It is demonstrated that a trade-off is possible between test quality,
test time, and silicon area. In contrast to BIST schemes based on test point
insertion no modifications of the circuit under test are required, complete
fault efficiency is guaranteed, and the impact on the design process is
minimized.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-45&engl=0}
}
@inproceedings {INPROC-2000-44,
author = {Silvia Chiusano and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{Non-Intrusive BIST for Systems-on-a-Chip}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {644--651},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894259},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The term functional BIST describes a test method to control functional modules
so that they generate a deterministic test set, which targets structural faults
within other parts of the system. It is a promising solution for self-testing
complex digital systems at reduced costs in terms of area overhead and
performance degradation. While previous work mainly investigated the use of
functional modules for generating pseudo-random and pseudo-exhaustive test
patterns, the present paper shows that a variety of modules can also be used as
a deterministic test pattern generator via an appropriate reseeding strategy.
This method enables a BIST technique that does not introduce additional
hardware like test points and test registers into combinational and pipelined
modules under test. The experimental results prove that the reseeding method
works for accumulator based structures, multipliers, or encryption modules as
efficiently as for the classic linear feedback shift registers, and some times
even better.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-44&engl=0}
}
@inproceedings {INPROC-2000-43,
author = {Sybille Hellebrand and Hua-Guo Liang and Hans-Joachim Wunderlich},
title = {{A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {778--784},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894274},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a
programmable Johnson counter and is called folding counter. Both the
theoretical background and practical algorithms are presented to characterize a
set of deterministic test cubes by a reasonably small number of seeds for a
folding counter. Combined with classical techniques for test width compression
and with pseudo-random pattern generation these new techniques provide an
efficient and flexible solution for scan-based BIST.. Experimental results show
that the proposed scheme outperforms previously published approaches based on
the reseeding of LFSRs or Johnson counters.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-43&engl=0}
}
@article {ART-2000-18,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Partial Scan}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {16},
number = {3},
pages = {169--177},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2000},
issn = {0923-8174},
doi = {10.1023/A:1008374811502},
keywords = {deterministic scan-based BIST; partial scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An efficient deterministic BIST scheme based on partial scan chains together
with a scan selection algorithm tailored for BIST is presented. The algorithm
determines a minimum number of flipflops to be scannable so that the remaining
circuit has a pipeline-like structure. Experiments show that scanning less
flipflops may even decrease the hardware overhead for the on-chip pattern
generator besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2000-18&engl=0}
}
@article {ART-2000-17,
author = {Stefan Gerstendoerfer and Hans-Joachim Wunderlich},
title = {{Minimized Power Consumption for Scan-Based BIST}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {16},
number = {3},
pages = {203--212},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2000},
issn = {0923-8174},
doi = {10.1023/A:1008383013319},
keywords = {deterministic scan-based BIST; partial scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Power consumption of digital systems may increase significantly during testing.
In this paper, systems equipped with a scan-based built-in self-test like the
STUMPS architecture are analyzed, the modules and modes with the highest power
consumption are identified, and design modifications to reduce power
consumption are proposed. The design modifications include some gating logic
for masking the scan path activity during shifting, and the synthesis of
additional logic for suppressing random patterns which do not contribute to
increase the fault coverage. These design changes reduce power consumption
during BIST by several orders of magnitude, at very low cost in terms of area
and performance.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2000-17&engl=0}
}