@inproceedings {INPROC-2016-55,
author = {Felix Baumann and Oliver Kopp and Dieter Roller},
title = {{Universal API for 3D Printers}},
booktitle = {INFORMATIK},
editor = {Heinrich C. Mayr and Martin Pinzger},
publisher = {Gesellschaft f{\"u}r Informatik e.V. (GI)},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
series = {Lecture Notes in Informatics (LNI)},
volume = {P-259},
pages = {1611--1622},
type = {Konferenz-Beitrag},
month = {September},
year = {2016},
isbn = {978-3-88579-653-4},
language = {Englisch},
cr-category = {H.4.1 Office Automation},
ee = {http://subs.emis.de/LNI/Proceedings/Proceedings259/1611.pdf,
http://www.informatik2016.de/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Architektur von Anwendungssystemen;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnergest{\"u}tzte Ingenieursysteme},
abstract = {With this research we propose the implementation of a overlay restful API for
3D printers to expose these machines to the Internet for utilization within
cloud services. This is to abstract the underlying communication structure and
means for accessing and controlling a 3D printer resource which is performed in
one of three ways. The ®rst method of accessing and controlling a 3D printer
is via a proprietary protocol or a printer driver in Microsoft Windows. The
second method is the control via a USB-serial connection between a controlling
computer and the printer resource. This protocol can either be proprietary or
based on open standards like GCODE (ISO 6983-1:2009). The third method of
control is based on physical storage devices attached to the printer with
machining instructions stored on them. This research excludes the communication
and control means involving proprietary protocols or drivers due complexity
restrictions within the implementation. The approach is designed with
extensibility in mind so that future access to proprietary protocols can be
added to the control API. Printer resources with only the third control method
available are also excluded from this research as they are currently lacking
the capability to be remotely controlled. This work describes the design and
implementation of an abstraction API layer between varying soft- and hardware
components with an extensible architecture for future hard- and software
components for within the domain of Additive Manufacturing (AM).},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2016-55&engl=0}
}
@inproceedings {INPROC-2002-47,
author = {Arnaud Virazel and Hans-Joachim Wunderlich},
title = {{Power Conscious BIST Approaches}},
booktitle = {3. VIVA Schwerpunkt-Kolloquium; Chemnitz, Germany; 18. - 19. March 2002},
publisher = {-},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {128--135},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2002},
isbn = {3-00-008 995-0},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The System-On-Chip (SOC) revolution has brought some new challenges to both
design and test engineers. The most important challenges of today’s VLSI
systems testing are linked to test cost, defect coverage and power dissipation.
Implementing a self-testable system may reduce test costs as expensive external
high performance test equipment is not required and it may increase defect
coverage as testing is performed at system speed. Unfortunately, the classic
BIST approaches lead to a significant increase of power consumption compared to
the system mode and even compared to external testing. The paper will review
required changes to be applied to classic BIST techniques for power reduction.
A recently developed new BIST approach called functional BIST is introduced and
its consequences for power dissipation are discussed.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-47&engl=0}
}
@inproceedings {INPROC-2002-45,
author = {Lars Schaefer and Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{RESPIN++ - Deterministic Embedded Test}},
booktitle = {Proceedings of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {139--146},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2002},
isbn = {0-7695-1715-3},
issn = {1530-1877},
doi = {10.1109/ETW.2002.1029637},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {RESPIN++ is a deterministic embedded test method tailored to system chips,
which implement scan test at core level. The scan chains of one core of the
system-on-a-chip are reused to decompress the patterns for another core. To
implement the RESPIN++ test architecture only a few gates need to be added to
the test wrapper. This will not affect the critical paths of the system. The
RESPIN++ method reduces both test data volume and test application time up to
one order of magnitude per core compared to storing compacted test patterns on
the ATE. If several cores may be tested concurrently, test data volume and test
application time for the complete system test may be reduced even further. This
paper presents the RESPIN++ test architecture and a compression algorithm for
the architecture.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-45&engl=0}
}
@inproceedings {INPROC-2002-44,
author = {Harald Vranken and Florian Meister and Hans-Joachim Wunderlich},
title = {{Combining Deterministic Logic BIST with Test Point Insertion}},
booktitle = {Proceedings of the 7th European Test Workshop (ETW'02); Korfu, Greece; May 26-29, 2002},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
series = {IEEE Computer Society Order Number},
volume = {PR01715},
pages = {105--110},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2002},
isbn = {0-7695-1715-3},
issn = {1530-1877},
doi = {10.1109/ETW.2002.1029646},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents a logic BIST approach which combines deterministic logic
BIST with test point insertion. Test points are inserted to obtain a first
testability improvement, and next a deterministic pattern generator is added to
increase the fault efficiency up to 100\%. The silicon cell area for the
combined approach is smaller than for approaches that apply a deterministic
pattern generator or test points only. The combined approach also removes the
classical limitations and drawbacks of test point insertion, such as failing to
achieve complete fault coverage and a complicated design flow. The benefits of
the combined approach are demonstrated in experimental results on a large
number of ISCAS and industrial circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-44&engl=0}
}
@inproceedings {INPROC-2001-82,
author = {Silvia Chiusano and Stefano di Carlo and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{On Applying the Set Covering Model to Reseeding}},
booktitle = {Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {156--160},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2001},
isbn = {0-7695-0993-2},
issn = {1530-1591},
doi = {10.1109/DATE.2001.915017},
keywords = {built-in self test; computational complexity; encoding; integrated circuit testing},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The Functional BIST approach is a rather new BIST technique based on exploiting
embedded system functionality to generate deterministic test patterns during
BIST. The approach takes advantages of two well-known testing techniques, the
arithmetic BIST approach and the reseeding method. The main contribution of the
present paper consists in formulating the problem of an optimal reseeding
computation as an instance of the set covering problem. The proposed approach
guarantees high flexibility, is applicable to different functional modules,
and, in general, provides a more efficient test set encoding then previous
techniques. In addition, the approach shorts the computation time and allows to
better exploiting the tradeoff between area overhead and global test length as
well as to deal with larger circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-82&engl=0}
}
@inproceedings {INPROC-2001-78,
author = {Alexander Irion and Gundolf Kiefer and Harald Vranken and Hans-Joachim Wunderlich},
title = {{Circuit Partitioning for Efficient Logic BIST Synthesis}},
booktitle = {Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE'01), Munich, Germany, March 12-16, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {86--91},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2001},
isbn = {0-7695-0993-2},
doi = {10.1109/DATE.2001.915005},
keywords = {circuit partitionig; deterministic BIST; divide-and-conquer},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A divide-and-conquer approach using circuit partitioning is presented, which
can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis
algorithms contain steps with a time complexity which increases more than
linearly with the circuit size. By extracting sub-circuits which are almost
constant in size, BIST synthesis for very large designs may be possible within
linear time. The partitioning approach does not require any physical
modifications of the circuit under test. Experiments show that significant
performance improvements can be obtained at the cost of a longer test
application time or a slight increase in silicon area for the BIST hardware.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-78&engl=0}
}
@inproceedings {INPROC-2001-77,
author = {Patrick Girard and Lois Guiller and Christian Landrault and Serge Pravossoudovitch and Hans-Joachim Wunderlich},
title = {{A Modified Clock Scheme for a Low Power BIST Test Pattern Generator}},
booktitle = {Proceedings of the 19th VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {306--311},
type = {Konferenz-Beitrag},
month = {April},
year = {2001},
isbn = {0-7695-1122-8},
issn = {1093-0167},
doi = {10.1109/VTS.2001.923454},
keywords = {Parallel BIST; Low-power Design; Test \& Low Power; Low Power BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper, we present a new low power BIST test pattern generator that
provides test vectors which can reduce the switching activity during test
operation. The proposed low power/energy BIST technique is based on a modified
clock scheme for the TPG and the clock tree feeding the TPG. Numerous
advantages can be found in applying such a technique. The fault coverage and
the test time are roughly the same as those achieved using a standard BIST
scheme. The area overhead is nearly negligible and there is no penalty on the
circuit delay. The proposed BIST scheme does not require any circuit design
modification beyond the parallel BIST technique, is easily implemented and has
low impact on the design time. It has been implemented based on an LFSR-based
TPG, but can also be designed using a cellular automata. Reductions of the
energy, average power and peak power consumption during test operation are up
to 94\%, 55\% and 48\% respectively for ISCAS and MCNC benchmark circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-77&engl=0}
}
@inproceedings {INPROC-2001-75,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Reusing Scan Chains for Test Pattern Decompression}},
booktitle = {Proceedings of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {124--132},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2001},
isbn = {0-7695-10 16-7},
issn = {1530-1877},
keywords = {system-on-a-chip; embedded test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a method for testing a system-on-a-chip by using a
compressed representation of the patterns on an external tester. The patterns
for a certain core under test are decompressed by reusing scan chains of cores
idle during that time. The method only requires a few additional gates in the
wrapper, while the mission logic is untouched. Storage and bandwidth
requirements for the ATE are reduced significantly.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-75&engl=0}
}
@inproceedings {INPROC-2001-74,
author = {Hua-Guo Liang and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST}},
booktitle = {``Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {894--902},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
issn = {1089-3539},
doi = {10.1109/TEST.2001.966712},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel architecture for scan-based mixed mode BIST is presented.
To reduce the storage requirements for the deterministic patterns it relies on
a two-dimensional compression scheme, which combines the advantages of known
vertical and hoizontal compression techniques. To reduce both the number of
patterns to be stored and the number of bits to be stored for each pattern,
deterministic test cubes are encoded as seeds of an LFSR (horizontal
compression), and the seeds are again compressed into seeds of a folding
counter sequence (vertical compression). The proposed BIST architecture is
fully compatible with standard scan esign, simple and flexible, so that sharing
between several logic cores is p0ossible. Experimental results show that the
proposed scheme requires less test data storage than previously publiched
approaches providing the same flexibility and scan compatibility.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-74&engl=0}
}
@inproceedings {INPROC-2001-73,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Tailoring ATPG for Embedded Testing}},
booktitle = {Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {530--537},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
issn = {1089-3539},
doi = {10.1109/TEST.2001.966671},
keywords = {Test Resource Partitioning; Systems-on-a-Chip; ATPG},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An automatic test pattern generation (ATPG) method is presented Testability for
a scan-based test architecture which min-imizes ATE storage requirements and
reduces the bandwidth be-tween the automatic test equipment (ATE) and the chip
under test. To generate tailored deterministic test patterns, a standard ATPG
tool performing dynamic compaction and allowing constraints on circuit inputs
is used. The combination of an appropriate test ar-chitecture and the tailored
test patterns reduces the test data vol-ume up to two orders of magnitude
compared with standard com-pacted test sets.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-73&engl=0}
}
@inproceedings {INPROC-2001-72,
author = {Michael Kessler and Gundolf Kiefer and Jens Leenstra and Knut Schuenemann and Thomas Schwarz and Hans-Joachim Wunderlich},
title = {{Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability}},
booktitle = {Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {461--469},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
issn = {1089-3539},
doi = {10.1109/TEST.2001.966663},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel hierarchical DfT methodology is presented which is
targeted to improve the delay fault testability for external testing and
scan-based BIST. After the partitioning of the design into high frequency
macros, the analysis for delay fault testability already starts in parallel
with the implementation at the macro level. A specification is generated for
each macro that defines the delay fault testing characteristics at the macro
boundaries. This specification is used to analyse and improve the delay fault
testability by improving the scan chain ordering at macro-level before the
macros are connected together into the total chip network. The hierarchical
methodology has been evaluated with the instruction window buffer core of an
out-of-order processor. It was shown that for this design practically no extra
hardware is required.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-72&engl=0}
}
@inproceedings {INPROC-2001-42,
author = {Michael Kessler and Gundolf Kiefer and Jens Leenstra and Knut Sch{\"u}nemann and Thomas Schwarz and Hans-Joachim Wunderlich},
title = {{Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability}},
booktitle = {Proceedings of the International Test Conference : ITC 2001 ; Baltimore, Maryland, October 30-November 1, 2001},
publisher = {IEEE Computer Society Press},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {461--469},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
keywords = {hierarchical; DfT; BIST; testability; scan chain reordering},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
C.1 Processor Architectures,
C.4 Performance of Systems},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Parallele und Verteilte H{\"o}chstleistungsrechner, Anwendersoftware;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel hierarchical DfT methodology is presented which is
targeted to improve the delay fault testability for external testing and
scan-based BIST. After the partitioning of the design into high frequency
macros, the analysis for delay fault testability already starts in parallel
with the implementation at the macro level. A specification is generated for
each macro that defines the delay fault testing characteristics at the macro
boundaries. This specification is used to analyse and improve the delay fault
testability by improving the scan chain ordering at macro-level before the
macros are connected together into the total chip network. The hierarchical
methodology has been evaluated with the instruction window buffer core of an
out-of-order processor. It was shown that for this design practically no extra
hardware is required.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-42&engl=0}
}
@inproceedings {INPROC-2000-46,
author = {Silvia Cataldo and Silvia Chiusano and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{Optimal Hardware Pattern Generation for Functional BIST}},
booktitle = {Proceedings of the 3rd Conference on Design and Test in Europe (DATE), Paris, France, March 27-30, 2000},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {292--297},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2000},
isbn = {0-7695-0537-6},
issn = {1530-1591},
doi = {10.1109/DATE.2000.840286},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Functional BIST is a promising solution for self-testing complex digital
systems at reduced costs in terms of area and performance degradation. The
present paper addresses the computation of optimal seeds for an arbitrary
sequential module to be used as hardware test pattern generator. Up to now,
only linear feedback shift registers and accumulator based structures have been
used for deterministic test pattern generation by reseeding. In this paper, a
method is proposed which can be applied to general finite state machines.
Nevertheless the method is absolutely general, for sake of comparison with
previous approaches, in this paper an accumulator based unit is assumed as
pattern generator module. Experiments prove the effectiveness of the approach
which outperforms previous results for accumulators, in terms of test size and
test time, without sacrifying the fault detection capability.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-46&engl=0}
}
@inproceedings {INPROC-2000-45,
author = {Gundolf Kiefer and Harald Vranken and Erik Jan Marinessen and Hans-Joachim Wunderlich},
title = {{Application of Deterministic Logic BIST on Industrial Circuits}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 200},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {105--114},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894197},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {We present the application of a deterministic logic BIST scheme on
state-of-the-art industrial circuits. Experimental results show that complete
fault coverage can be achieved for industrial circuits up to 100K gates with
10,000 test patterns, at a total area cost for BIST hardware of typically
5\%-15\%. It is demonstrated that a trade-off is possible between test quality,
test time, and silicon area. In contrast to BIST schemes based on test point
insertion no modifications of the circuit under test are required, complete
fault efficiency is guaranteed, and the impact on the design process is
minimized.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-45&engl=0}
}
@inproceedings {INPROC-2000-44,
author = {Silvia Chiusano and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{Non-Intrusive BIST for Systems-on-a-Chip}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {644--651},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894259},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The term functional BIST describes a test method to control functional modules
so that they generate a deterministic test set, which targets structural faults
within other parts of the system. It is a promising solution for self-testing
complex digital systems at reduced costs in terms of area overhead and
performance degradation. While previous work mainly investigated the use of
functional modules for generating pseudo-random and pseudo-exhaustive test
patterns, the present paper shows that a variety of modules can also be used as
a deterministic test pattern generator via an appropriate reseeding strategy.
This method enables a BIST technique that does not introduce additional
hardware like test points and test registers into combinational and pipelined
modules under test. The experimental results prove that the reseeding method
works for accumulator based structures, multipliers, or encryption modules as
efficiently as for the classic linear feedback shift registers, and some times
even better.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-44&engl=0}
}
@inproceedings {INPROC-2000-43,
author = {Sybille Hellebrand and Hua-Guo Liang and Hans-Joachim Wunderlich},
title = {{A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {778--784},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894274},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a
programmable Johnson counter and is called folding counter. Both the
theoretical background and practical algorithms are presented to characterize a
set of deterministic test cubes by a reasonably small number of seeds for a
folding counter. Combined with classical techniques for test width compression
and with pseudo-random pattern generation these new techniques provide an
efficient and flexible solution for scan-based BIST.. Experimental results show
that the proposed scheme outperforms previously published approaches based on
the reseeding of LFSRs or Johnson counters.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-43&engl=0}
}
@inproceedings {INPROC-1999-53,
author = {Vyacheslav N. Yarmolik and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Symmetric Transparent BIST for RAMs}},
booktitle = {Proceedings of the 2nd Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 9-12, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {702--708},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {1999},
isbn = {0-7695-0078-1},
doi = {10.1109/DATE.1999.761206},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper introduces the new concept of symmetric transparent BIST for RAMs.
This concept allows to skip the signature prediction phase of conventional
transparent BIST approaches and therefore yields a significant reduction of
test time. The hardware cost and the fault coverage of the new scheme remain
comparable to that of a traditional transparent BIST scheme. In many cases,
experimental studies even show a higher fault coverage obtained in shorter test
time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-53&engl=0}
}
@inproceedings {INPROC-1999-52,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Alexander Ivaniuk and Yuri Klimets and Vyacheslav N. Yarmolik},
title = {{Error Detecting Refreshment for Embedded DRAMs}},
booktitle = {Proceedings of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 25-29, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {384--390},
type = {Konferenz-Beitrag},
month = {April},
year = {1999},
isbn = {0-7695-0146-X},
issn = {1093-0167},
doi = {10.1109/VTEST.1999.766693},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents a new technique for on-line consistency checking of
embedded DRAMs. The basic idea is to use the refresh cycle for concurrently
computing a test characteristic of the memory contents and compare it to a
precomputed reference characteristic. Experiments show that the proposed
technique significantly reduces the time between the occurrence of an error and
its detection (error detection latency). It also achieves a very high error
coverage at low hardware costs. Therefore it perfectly complements standard
on-line checking approaches relying on error detecting codes, where the
detection of certain types of errors is guaranteed, but only during READ
operations accessing the erroneous data.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-52&engl=0}
}
@inproceedings {INPROC-1999-51,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Partial Scan}},
booktitle = {Proceedings of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {110--117},
type = {Konferenz-Beitrag},
month = {Mai},
year = {1999},
isbn = {0-7695-0390-X},
doi = {10.1109/ETW.1999.804415},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An efficient deterministic BIST scheme based on partial scan chains together
with a scan selection algorithm tailored for BIST is presented. The algorithm
determines a minimum number of flipflops to be scannable so that the remaining
circuit has a pipeline-like structure. Experiments show that scanning less
flipflops may even decrease the hardware overhead for the on-chip pattern
generator besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-51&engl=0}
}
@inproceedings {INPROC-1999-50,
author = {Vyacheslav N. Yarmolik and I.V. Bykov and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms}},
booktitle = {Proceedings of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999},
address = {Berlin / Heidelberg},
publisher = {Springer},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {339--350},
type = {Konferenz-Beitrag},
month = {September},
year = {1999},
isbn = {978-3-540-66483-3},
isbn = {ISSN 0302-9743},
doi = {10.1007/3-540-48254-7_23},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a new approach to transparent BIST for word-oriented RAMs
which is based on the transformation of March transparent test algorithms to
the symmetric versions. This approach allows to skip the signature prediction
phase inherent to conventional transparent memory testing and therefore to
significantly reduce test time. The hardware overhead and fault coverage of the
new BIST scheme are comparable to the conventional transparent BIST structures.
Experimental results show that in many cases the proposed test techniques
achieve a higher fault coverage in shorter test time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-50&engl=0}
}
@inproceedings {INPROC-1999-49,
author = {Stefan Gerstendoerfer and Hans-Joachim Wunderlich},
title = {{Minimized Power Consumption for Scan-Based BIST}},
booktitle = {Proceedings of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {77--84},
type = {Konferenz-Beitrag},
month = {September},
year = {1999},
isbn = {0-7803-5753-1},
issn = {1089-3539},
doi = {10.1109/TEST.1999.805616},
keywords = {BIST; Low Power; Power consumption},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Power consumption of digital systems may increase significantly during testing.
In this paper, systems equipped with a scan-based built-in self-test like the
STUMPS architecture are analyzed, the modules and modes with the highest power
consumption are identified, and design modifications to reduce power
consumption are proposed. The design modifications include some gating logic
for masking the scan path activity during shifting, and the synthesis of
additional logic for suppressing random patterns which do not contribute to
increase the fault coverage. These design changes reduce power consumption
during BIST by several orders of magnitude, at very low cost in terms of area
and performance.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-49&engl=0}
}
@inproceedings {INPROC-1998-43,
author = {Vyacheslav N. Yarmolik and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs}},
booktitle = {Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE), Paris, France,February 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {173--179},
type = {Konferenz-Beitrag},
month = {Februar},
year = {1998},
isbn = {0-8 186-8359-7},
isbn = {},
doi = {10.1109/DATE.1998.655853},
keywords = {built-in self test; data compression; integrated circuit testing; random-access storage},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {After write operations, BIST schemes for RAMs relying on signature analysis
must compress the entire memory contents to update the reference signature.
This paper introduces a new scheme for output data compression which avoids
this overhead while retaining the benefits of signature analysis. The proposed
technique is based on a new memory characteristic derived as the modulo-2 sum
of all addresses pointing to non-zero cells. This characteristic can be
adjusted concurrently with write operations by simple EXOR-operations on the
initial characteristic and on the addresses affected by the change.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-43&engl=0}
}
@inproceedings {INPROC-1998-42,
author = {Andre Hertwig and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Fast Self-Recovering Controllers}},
booktitle = {Proceedings of the 16th IEEE VLSI Test Symposium (VTS), Monterey, CA, April 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {296--302},
type = {Konferenz-Beitrag},
month = {April},
year = {1998},
isbn = {0-8 186-8436-4},
issn = {1093-0167},
doi = {10.1109/VTEST.1998.670883},
keywords = {FSM synthesis; fault-tolerance; checkpointing; performance-driven synthesis},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A fast fault-tolerant controller structure is presented, which is capable of
recovering from transient faults by performing a rollback operation in
hardware.
The proposed fault-tolerant controller structure utilizes the rollback hardware
also for system mode and this way achieves performance improvements of more
than 50\% compared to controller structures made fault-tolerant by conventional
techniques, while the hardware overhead is often negligible. The proposed
approach is compatible with state-of-the-art methods for FSM decomposition,
state encoding and logic synthesis.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-42&engl=0}
}
@inproceedings {INPROC-1998-41,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Accumulator Based Deterministic BIST}},
booktitle = {Proceedings of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {412--421},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {1998},
isbn = {0-7803-5092-8},
issn = {1089-3539},
doi = {10.1109/TEST.1998.743181},
keywords = {BIST; hardware pattern generator; embedded cores},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Most built-in self test (BIST) solutions require specialized test pattern
generation hardware which may introduce significant area overhead and
performance degradation. Recently, some authors proposed test pattern
generation on chip by means of functional units also used in system mode like
adders or multipliers. These schemes generate pseudo-random or
pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under
test contains random pattern resistant faults a deterministic test pattern
generator is necessary to obtain complete fault coverage.
In this paper it is shown that a deterministic test set can be encoded as
initial values of an accumulator based structure, and all testable faults can
be detected within a given test length by carefully selecting the seeds of the
accumulator. A ROM is added for storing the seeds, and the control logic of the
accumulator is modified. In most cases the size of the ROM is less than the
size required by traditional LFSR-based reseeding approaches.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-41&engl=0}
}
@inproceedings {INPROC-1998-40,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Multiple Scan Chains}},
booktitle = {Proceedings of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {1057--1064},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {1998},
isbn = {0-7803-5092-8},
issn = {1089-3539},
doi = {10.1109/TEST.1998.743304},
keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented.
A procedure is described for synthesizing a pattern generator which stimulates
all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach
while better or even complete fault coverage is obtained at the same time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-40&engl=0}
}
@inproceedings {INPROC-1998-39,
author = {Vyacheslav N. Yarmolik and Yuri Klimets and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{New Transparent RAM BIST Based on Self-Adjusting Output Data Compression}},
booktitle = {Proceedings of Design \& Diagnostics of Electronic Circuits \& Systems (DDECS), Szczyrk, Poland, September 1998},
address = {Gliwice},
publisher = {Silesian Techn. Univ. Press},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {27--33},
type = {Konferenz-Beitrag},
month = {September},
year = {1998},
isbn = {83-90840-96-0},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The new memory transparent BIST technique is proposed in this paper. It has
more higher fault coverage compare to classical transparent technique. Also
this technique decreases the test complexity up to 50\% for the most of march
tests.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-39&engl=0}
}
@inproceedings {INPROC-1998-38,
author = {Madhavi Karkal and Nur A. Touba and Hans-Joachim Wunderlich},
title = {{Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST}},
booktitle = {Proceedings of the 7th Asian Test Symposium (ATS), Singapore, December 2-4, 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {492--499},
type = {Konferenz-Beitrag},
month = {Dezember},
year = {1998},
isbn = {0-8 186-8277-9},
issn = {1081-7735},
doi = {10.1109/ATS.1998.741662},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In mixed-mode BIST, deterministic test patterns are generated with on-chip
hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed
by the pseudo-random patterns. While previous work in mixed-mode BIST has
focussed on developing hardware schemes for more efficiently encoding a given
set of deterministic patterns (generated by a conventional ATPG procedure), the
approach taken in this paper is to improve the encoding efficiency (and hence
reduce hardware overhead) by specially selecting a set of deterministic
patterns for the r.p.r. faults that can be efficiently encoded. A special ATPG
procedure is described for finding test patterns for the r.p.r. faults that are
correlated (have the same logic value) in many bit positions. Such test
patterns can be efficiently encoded with one of the many ``bit-fixing'' schemes
that have been described in the literature. Results are shown for different
bit-fixing schemes which indicate dramatic reductions in BIST overhead can be
achieved by using the proposed ATPG procedure to select which test patterns to
encode.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-38&engl=0}
}
@inproceedings {INPROC-1997-32,
author = {Andre Hertwig and Hans-Joachim Wunderlich},
title = {{Fast Controllers for Data Dominated Applications}},
booktitle = {Proceedings of the European Design \& Test Conference (ED\&TC), Paris, France, March 1997},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {84--89},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {1997},
isbn = {0-8186-7786-4},
isbn = {ISSN 1066-1409},
doi = {10.1109/EDTC.1997.582337},
keywords = {FSM synthesis, performance driven synthesis; synthesis of testable controllers},
language = {Englisch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A target structure for implementing fast edge-triggered control units is
presented. In many cases, the proposed controller is faster than a one-hot
encoded structure as its correct timing does not require master-slave
flip-flops even in the presence of unpredictable clocking skews. A synthesis
procedure is proposed which leads to a performance improvement of 40\% on
average for the standard benchmark set whereas the additional area is less than
25\% compared with conventional finite state machine (FSM) synthesis. The
proposed approach is compatible with the state-of-the-art methods for FSM
decomposition, state encoding and logic synthesis.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1997-32&engl=0}
}
@inproceedings {INPROC-1997-31,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Using BIST Conitrol for Pattern Generation}},
booktitle = {Proc. of the 28th IEEE International Test Conference (ITC), Washington, DC, November 1997},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {347--355},
type = {Konferenz-Beitrag},
month = {November},
year = {1997},
isbn = {0-7803-4209-7},
issn = {1089-3539},
doi = {10.1109/TEST.1997.639636},
keywords = {deterministic BIST; scan-based BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme is presented which requires less hardware overhead
than pseudo-random BIST but obtains better or even complete fault coverage at
the same time. It takes advantage of the fact that any autonomous BIST scheme
needs a BIST control unit for indicating the completion of the self-test at
least.
Hence, pattern counters and bit counters are always available, and they provide
information to be used for deterministic pattern generation by some additional
circuitry. This paper presents a systematic way for synthesizing a pattern
generator which needs less area than a 32-bit LFSR for random pattern
generation for all the benchmark circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1997-31&engl=0}
}
@inproceedings {INPROC-1996-22,
author = {Hans-Joachim Wunderlich and Gundolf Kiefer},
title = {{Bit-Flipping BIST}},
booktitle = {Proceedings of the ACM/IEEE International Conference on CAD-96 (ICCAD), San Jose, CA, November 1996},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {337--343},
type = {Konferenz-Beitrag},
month = {November},
year = {1996},
isbn = {0-8186-7597-7},
issn = {1063-6757},
doi = {10.1109/ICCAD.1996.569803},
keywords = {Mixed-Mode BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A scan-based BIST scheme is presented which guarantees complete fault coverage
with very low hardware overhead. A probabilistic analysis shows that the output
of an LFSR which feeds a scan path has to be modified only at a few bits in
order to transform the random patterns into a complete test set. These
modifications may be implemented by a bit-flipping function which has the
LFSR-state as an input, and flips the value shifted into the scan path at
certain times. A procedure is described for synthesizing the additional
bit-flipping circuitry, and the experimental results indicate that this
mixed-mode BIST scheme requires less hardware for complete fault coverage than
all the other scan-based BIST approaches published so far.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1996-22&engl=0}
}
@article {ART-2002-14,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Reusing Scan Chains for Test Pattern Decompression}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {18},
number = {2},
pages = {231--240},
type = {Artikel in Zeitschrift},
month = {April},
year = {2002},
isbn = {0923-8174},
doi = {10.1023/A:1014968930415},
keywords = {system-on-a-chip; embedded test; BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a method for testing a system-on-a-chip by using a
compressed representation of the patterns on an external tester. The patterns
for a certain core under test are decompressed by reusing scan chains of cores
idle during that time. The method only requires a few additional gates in the
wrapper, while the mission logic is untouched. Storage and bandwidth
requirements for the ATE are reduced significantly.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-14&engl=0}
}
@article {ART-2002-11,
author = {Hua-Guo Liang and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {18},
number = {2},
pages = {157--168},
type = {Artikel in Zeitschrift},
month = {April},
year = {2002},
issn = {0923-8174},
doi = {10.1023/A:1014993509806},
keywords = {BIST; deterministic BIST; store and generate schemes; test data compression},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel architecture for scan-based mixed mode BIST is presented.
To reduce the storage requirements for the deterministic patterns it relies on
a two-dimensional compression scheme, which combines the advantages of known
vertical and hoizontal compression techniques. To reduce both the number of
patterns to be stored and the number of bits to be stored for each pattern,
deterministic test cubes are encoded as seeds of an LFSR (horizontal
compression), and the seeds are again compressed into seeds of a folding
counter sequence (vertical compression). The proposed BIST architecture is
fully compatible with standard scan esign, simple and flexible, so that sharing
between several logic cores is p0ossible. Experimental results show that the
proposed scheme requires less test data storage than previously publiched
approaches providing the same flexibility and scan compatibility.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-11&engl=0}
}
@article {ART-2002-10,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Alexander A. Ivaniuk and Yuri V. Klimets and Vyacheslav N. Yarmolik},
title = {{Efficient On- and Off-Line Testing of Embedded DRAMs}},
journal = {IEEE Transaction on Computers},
publisher = {IEEE Computer Society},
volume = {51},
number = {7},
pages = {801--809},
type = {Artikel in Zeitschrift},
month = {Juli},
year = {2002},
issn = {0018-9340},
doi = {10.1109/TC.2002.1017700},
keywords = {Embedded memories; systems-on-a-chip; online checking; BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents an integrated approach for both built-in online and offline
testing of embedded DRAMs. It is based on a new technique for output data
compression which offers the same benefits as signature analysis during offline
test, but also supports efficient online consistency checking. The initial
fault-free memory contents are compressed to a reference characteristic and
compared to test characteristics periodically. The reference characteristic
depends on the memory contents, but unlike similar characteristics based on
signature analysis, it can be easily updated concurrently with WRITE
operations. This way, changes in memory do not require a time consuming
recomputation. The respective test characteristics can be efficiently computed
during the periodic refresh operations of the dynamic RAM. Experiments show
that the proposed technique significantly reduces the time between the
occurrence of an error and its detection (error detection latency). Compared to
error detecting codes (EDC) it also achieves a significantly higher error
coverage at lower hardware costs. Therefore, it perfectly complements standard
online checking approaches relying on EDC, where the concurrent detection of
certain types of errors is guaranteed, but only during READ operations
accessing the erroneous data.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-10&engl=0}
}
@article {ART-2002-09,
author = {Patrick Girard and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel and Hans-Joachim Wunderlich},
title = {{High Defect Coverage with Low Power Test Sequences in a BIST Environment}},
journal = {IEEE Design and Test of Computers},
publisher = {IEEE Computer Society},
volume = {19},
number = {5},
pages = {44--52},
type = {Artikel in Zeitschrift},
month = {September},
year = {2002},
issn = {0740-7475},
doi = {10.1109/MDT.2002.1033791},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A new technique, random single-input change (RSIC) test generation, generates
low-power test patterns that provide a high level of defect coverage during
low-power BIST of digital circuits. The authors propose a parallel BIST
implementation of the RSIC generator and analyze its area-overhead impact.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-09&engl=0}
}
@article {ART-2001-19,
author = {Gundolf Kiefer and Harald Vranken and Erik Jan Marinessen and Hans-Joachim Wunderlich},
title = {{Application of deterministic logic BIST on industrial circuits}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {17},
number = {3},
pages = {351--362},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2001},
isbn = {0923-8174},
doi = {10.1023/A:1012283800306},
keywords = {logic BIST; industrial applications; scan-based BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {We present the application of a deterministic logic BIST scheme based on
bit-flipping on state-of-the-art industrial circuits. Experimental results show
that complete fault coverage can be achieved for industrial circuits up to 100
K gates with 10,000 test patterns, at a total area cost for BIST hardware of
typically 5\% - 15\%. It is demonstrated that a trade-off is possible between
test quality, test time, and silicon area. In contrast to BIST schemes based on
test point insertion no modifications of the circuit under test are required,
complete fault efficiency is guaranteed, and the impact on the design process
is minimized.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2001-19&engl=0}
}
@article {ART-2001-17,
author = {Sybille Hellebrand and Hua-Guo Liang and Hans-Joachim Wunderlich},
title = {{A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {17},
number = {3/4},
pages = {341--349},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2001},
issn = {0923-8174},
doi = {10.1023/A:1012279716236},
keywords = {BIST; deterministic BIST; store and generate schemes},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a
programmable Johnson counter and is called folding counter. Both the
theoretical background and practical algorithms are presented to characterize a
set of deterministic test cubes by a reasonably small number of seeds for a
folding counter. Combined with classical techniques for test width compression
and with pseudo-random pattern generation these new techniques provide an
efficient and flexible solution for scan-based BIST. Experimental results show
that the proposed scheme outperforms previously published approaches based on
the reseeding of LFSRs or Johnson counters.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2001-17&engl=0}
}
@article {ART-2000-18,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Partial Scan}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {16},
number = {3},
pages = {169--177},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2000},
issn = {0923-8174},
doi = {10.1023/A:1008374811502},
keywords = {deterministic scan-based BIST; partial scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An efficient deterministic BIST scheme based on partial scan chains together
with a scan selection algorithm tailored for BIST is presented. The algorithm
determines a minimum number of flipflops to be scannable so that the remaining
circuit has a pipeline-like structure. Experiments show that scanning less
flipflops may even decrease the hardware overhead for the on-chip pattern
generator besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2000-18&engl=0}
}
@article {ART-2000-17,
author = {Stefan Gerstendoerfer and Hans-Joachim Wunderlich},
title = {{Minimized Power Consumption for Scan-Based BIST}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {16},
number = {3},
pages = {203--212},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2000},
issn = {0923-8174},
doi = {10.1023/A:1008383013319},
keywords = {deterministic scan-based BIST; partial scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Power consumption of digital systems may increase significantly during testing.
In this paper, systems equipped with a scan-based built-in self-test like the
STUMPS architecture are analyzed, the modules and modes with the highest power
consumption are identified, and design modifications to reduce power
consumption are proposed. The design modifications include some gating logic
for masking the scan path activity during shifting, and the synthesis of
additional logic for suppressing random patterns which do not contribute to
increase the fault coverage. These design changes reduce power consumption
during BIST by several orders of magnitude, at very low cost in terms of area
and performance.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2000-17&engl=0}
}
@article {ART-1999-10,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Multiple Scan Chains}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {14},
number = {1-2},
pages = {85--93},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {1999},
issn = {0923-8174},
doi = {10.1023/A:1008353423305},
keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented.
A procedure is described for synthesizing a pattern generator which stimulates
all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach
while better or even complete fault coverage is obtained at the same time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1999-10&engl=0}
}
@article {ART-1998-15,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Andre Hertwig},
title = {{Mixed-Mode BIST Using Embedded Processors}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {12},
number = {1-2},
pages = {127--138},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {1998},
issn = {0923-8174},
doi = {10.1023/A:1008294125692},
keywords = {BIST; random pattern testing; deterministic BIST; embedded systems},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In complex systems, embedded processors may be used to run software for test
pattern generation and response evaluation. For system components which are not
completely random pattern testable, the test programs have to generate
deterministic patterns after random testing. Usually the random test part of
the program requires long run times whereas the part for deterministic testing
has high memory requirements.
In this paper it is shown that an appropriate selection of the random pattern
test method can significantly reduce the memory requirements of the
deterministic part. A new, highly efficient scheme for software-based random
pattern testing is proposed, and it is shown how to extend the scheme for
deterministic test pattern generation. The entire test scheme may also be used
for implementing a scan based BIST in hardware.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-15&engl=0}
}
@article {ART-1998-14,
author = {Albrecht P. Stroele and Hans-Joachim Wunderlich},
title = {{Hardware-Optimal Test Register Insertion}},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
publisher = {IEEE Circuits and Systems Society},
volume = {17},
number = {6},
pages = {531--539},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {1998},
issn = {0278-0070},
doi = {10.1109/43.703833},
keywords = {BILBO; built-in self-test; CBILBO; test register insertion},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Implementing a built-in self-test by a ``test per clock'' scheme offers
advantages concerning fault coverage, detection of delay faults and test
application time. Such a scheme is implemented by test registers, for instance
BILBOs or CBILBOs, which are inserted into the circuit structure at appropriate
places. An algorithm is presented which is able to find the cost optimal
placement of test registers for nearly all the ISCAS'89 sequential benchmark
circuits, and a suboptimal solution with slightly higher costs is obtained for
all the circuits within a few minutes of computing time. The algorithm can also
be applied to the Minimum Feedback Vertex Set problem in partial scan desing,
and an optimal solution is found for all the benchmark circuits.
The proveably optimal solutions for the benchmark circuits mainly use CBILBOs
which can simultaneously generate test patterns and compact test responses.
Hence, test scheduling is not required, test control is simplified, and test
application time is reduced.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-14&engl=0}
}
@article {ART-1998-13,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Andre Hertwig},
title = {{Synthesizing fast, online-testable control units}},
journal = {IEEE Design \& Test of Computers,},
publisher = {IEEE Computer Society},
volume = {15},
number = {4},
pages = {36--41},
type = {Artikel in Zeitschrift},
month = {Oktober},
year = {1998},
issn = {0740-7475},
doi = {10.1109/54.735925},
keywords = {error detection; finite state machines; logic testing},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The authors present the self-checking bypass pipeline, an online-testable
controller structure for data-dominated applications. For most circuits in a
standard benchmark set, this structure leads to a performance improvement of
more than 30\% with an area overhead less than 15\% that of conventional
online-testable finite-state machines},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-13&engl=0}
}
@article {ART-1998-12,
author = {Hans-Joachim Wunderlich},
title = {{BIST for Systems-on-a-Chip}},
journal = {INTEGRATION, The VLSI Journal},
publisher = {Elsevier Science B.V},
volume = {26},
number = {1-2},
pages = {55--78},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {1998},
issn = {0167-9260},
doi = {10.1016/S0167-9260(98)00021-2},
keywords = {BIST; Systems-on-chip; Deterministic BIST; Functional BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An increasing part of microelectronic systems is implemented on the basis of
predesigned and preverified modules, so-called cores, which are reused in many
instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many
other functions, and built-in self-test ist the appropriate method for testing
complex systems composed of different cores In this paper, we overview BIST
methods for different types of cores and present advanced BIST solutions.
Special emphasis is put on deterministic BIST methods as they do not require
any modifications of the core under test and help to protect intellectual
property (IP).},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-12&engl=0}
}
@book {BOOK-1998-01,
author = {Kerstin Schneider (Hrsg.) and Hiltrud Betz and Cora Burger and Volker Claus and Waltraud Schweikhardt},
title = {{Die Informatik AG - Telekooperation.}},
address = {Stuttgart},
publisher = {B.G. Teubner-Verlag},
pages = {158},
type = {Buch},
month = {Januar},
year = {1998},
isbn = {3-519-12194-8},
keywords = {Studieninformation; Frauenf{\"o}rderung; gender; computer science},
language = {Deutsch},
cr-category = {K.3 Computers and Education},
ee = {http://www.informatik.uni-stuttgart.de/fakultaet/frauen/frauen.html,
http://medoc.informatik.uni-stuttgart.de/~medoc/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Parallele und Verteilte H{\"o}chstleistungsrechner, Anwendersoftware (Prof. Reuter);
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Formale Konzepte;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Programmiersprachen und {\"U}bersetzerbau;
Universit{\"a}t Stuttgart, Institut f{\"u}r Parallele und Verteilte H{\"o}chstleistungsrechner, Verteilte Systeme;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Visualisierung und Interaktive Systeme},
abstract = {(not available)},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=BOOK-1998-01&engl=0}
}