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- Abdelfattah, Mohamed: Evaluation of advanced techniques for structural FPGA self-test, Masterarbeit Nr. 11, 2011.
- Boktor, Andrew: Development of an Error Detection and Recovery Technique for a SPARC V8 Processor in FPGA Technology, Masterarbeit Nr. 3097, 2011.
- Buntoro, David Prasetyo: Modeling of Design-for-test infrastructure in complex Systems-on-chips, Masterarbeit Nr. 3304, 2012.
- Cook, Alejandro: FPGA Emulation of a GALS Network-on-Chip Interconnection, Masterarbeit Nr. 2813, 2009.
- Dallou, Tamer: Software-Based Self-Test For SUN's UltraSPARC T2 SoC, Masterarbeit Nr. 2955, 2010.
- Georgiev, Zdravko: Simulation-Based Analysis For NBTI Degradation In Combinational CMOS VLSI Circuits, Masterarbeit Nr. 3436, 2013.
- Gosswami, Bishwajit Mohan: Implementing Density Functional Theory (DFT)Methods on Many-core GPGPU Accelerators by Bishwajit Mohan Gosswami, Masterarbeit Nr. 3221, 2011.
- Guo, Xiao Lei: Development of a Generic Gateway for an Event controlled Communication based on a reconfigurable FPGA Architecture with a Soft-core Microcontroller, Masterarbeit Nr. 6, 2005.
- Kasimoglu, Ozan: Eclipse Based Frontend to Layout Navigation for Precision Diagnosis, Masterarbeit Nr. 2668, 2007.
- Lancho, Antonio Fernández: LEON-based Multiprocessor System on FPGA netweork, Masterarbeit Nr. 6, 2008.
- Lui, Shuo: Evaluation of FPGA/Host Communication Based on Ethernet, Masterarbeit Nr. 2946, 2010.
- Mascaraenhas, Rio: Fault Simulation of Cell-Based Designs using a FPGA-Based Emulation Machine, Masterarbeit Nr. 14, 2006.
- Mihalcut, Valentin: Adaptive Approximate Computing for Image Filtering using Dynamic Partial Reconfiguration, Masterarbeit Nr. 49, 2016.
- Murali, Deepthi: Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits, Masterarbeit Nr. 2016.
- Najmabadi, Seyyed Mahdi: Fault tolerant routing algorithm for fully- and partially-defective NoC switches, Masterarbeit Nr. 5, 2012.
- Nayak, Naresh: Accelerated Computation using Runtime Partial Reconfiguration, Masterarbeit Nr. 3491, 2013.
- Parajuli, Sambhavi: Partial Scan Design for Generation of Minimal Size, Balanced ATPG Models, Masterarbeit Nr. 13, 2007.
- Qu, Yijun: Design and Analysis of a Network-on-Chip Infrastructure, Masterarbeit Nr. 7, 2008.
- Rivera, Ramon Huerta: Design Guidelines to Perform Concurrent Test on Multiple Cores of a System-on-a-Chip, Masterarbeit Nr. 2, 2001.
- Sannikova, Anastasia: Embedding deterministic patterns in partial pseudo-exhaustive test, Masterarbeit Nr. 2, 2013.
- Sutantyo, Donny Kurnia: Investigation of the Impact of the Error Recovery Distribution on Power and Performance of Networks-on-Chip, Masterarbeit Nr. 5, 2009.
- Tamimi, Hiba: Investigating an Online Testing Technique for Dynamic Memories, Masterarbeit Nr. 15, 2005.
- Tilk, Maren: Sat-basierte Überprüfung der Fehlersicherheit von Schaltungen, Masterarbeit Nr. 8, 2015.
- Wang, Jiling: Online Self-Test Wrapper for Runtime-Reconfigurable Systems, Masterarbeit Nr. 3439, 2013.
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