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@inproceedings {INPROC-2007-88,
author = {Bernd Becker and Sybille Hellebrand and Bernd Straube and Hans-Joachim Wunderlich},
title = {{Test und Zuverl{\"a}ssigkeit nanoelektronischer Systeme}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 52), 1. GMM/GI/ITG-Fachtagung; M{\"u}nchen, Germany, 26.03. - 28.03.2007},
editor = {GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {52},
pages = {139--140},
type = {Konferenz-Beitrag},
month = {April},
year = {2007},
isbn = {978-3-8007-3023-0},
isbn = {docid: 463023018},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/463023018.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Neben der zunehmenden Anf{\"a}lligkeit gegen{\"u}ber Fertigungsfehlern bereiten
insbesondere vermehrte Parameterschwankungen, zeitabh{\"a}ngige Materialver{\"a}nderung
St{\"o}ranf{\"a}lligkeit w{\"a}hrend des Betriebs massive Probleme bei der
Qualit{\"a}tssicherung f{\"u}r nanoelektronische Systeme. F{\"u}r eine wirtschaftliche
Produktion und einen zuverl{\"a}ssigen Systembetrieb wird einerseits ein robuster
Entwurf unabdingbar, andererseits ist damit auch ein Paradigmenwechsel beim
Test erforderlich. Anstatt lediglich defektbehaftete Systeme zu erkennen und
auszusortieren, muss der Test bestimmen, ob ein System trotz einer gewissen
Menge von Fehlern funktionsf{\"a}hig ist, und die verbleibende Robustheit gegen{\"u}ber
St{\"o}rungen im Betrieb charakterisieren. Im Rahmen des Projekts RealTest werden
einheitliche Entwurfs- und Teststrategien entwickelt, die sowohl einen robusten
Entwurf als auch eine darauf abgestimmte Qualit{\"a}tssicherung unterst{\"u}tzen.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-88&engl=0}
}
@inproceedings {INPROC-2007-87,
author = {Michael E. Imhof and Christian G. Zoellin and Hans-Joachim Wunderlich and Nicolas Maeding and Jens Leenstra},
title = {{Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverl{\"a}ssigkeit und Ausbeute}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 52), 1. GMM/GI/ITG-Fachtagung; M{\"u}nchen, Germany, 26.03. - 28.03.2007},
editor = {GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {52},
pages = {69--76},
type = {Konferenz-Beitrag},
month = {April},
year = {2007},
isbn = {978-3-8007-3023-0},
isbn = {docid: 463023008},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/463023008.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Die stark erh{\"o}hte durchschnittliche und maximale Verlustleistung w{\"a}hrend des
Tests integrierter Schaltungen kann zu einer Beeintr{\"a}chtigung der Ausbeute bei
der Produktion sowie der Zuverl{\"a}ssigkeit im sp{\"a}teren Betrieb f{\"u}hren. Wir
stellen eine Testplanung f{\"u}r Schaltungen mit parallelen Pr{\"u}fpfaden vor, welche
die Verlustleistung w{\"a}hrend des Tests reduziert. Die Testplanung wird auf ein
{\"U}berdeckungsproblem abgebildet, das mit einem heuristischen L{\"o}sungsverfahren
effizient auch f{\"u}r gro{\ss}e Schaltungen gel{\"o}st werden kann. Die Effizienz des
vorgestellten Verfahrens wird sowohl f{\"u}r die bekannten Benchmarkschaltungen als
auch f{\"u}r gro{\ss}e industrielle Schaltungen demonstriert.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-87&engl=0}
}
@inproceedings {INPROC-2007-86,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Rio Mascarenhas and Juergen Schloeffel and Garbers Michael},
title = {{Synthesis of Irregular Combinational Functions with Large Don't Care Sets}},
booktitle = {Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, Stresa-Lago Maggiore, Italy, March 11-13, 2007},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {287--292},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2007},
isbn = {978-1-59593-605-9},
doi = {10.1145/1228784.1228856},
keywords = {logic synthesis; incompletely specified functions},
language = {Englisch},
cr-category = {B.6.3 Logic Design, Design Aids},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {A special logic synthesis problem is considered for Boolean functions which
have large don't care sets and are irregular. Here, a function ist considered
as irregular if the input assignments mapped to specified values ('1'or'0') are
randomly spread over the definition space. Such functions can be encounted in
the field of design for test. The proposed method uses ordered BDDs for logic
manipulations and generates freeBDD-like covers. For the considered benchmark
functions, implementations were found with the significant reduction of the
node/gate count as compared to SIS or the methodes offered by a
state-of-the-art BDD package.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-86&engl=0}
}
@inproceedings {INPROC-2007-79,
author = {Abdul-Wahid Hakmi and Hans-Joachim Wunderlich and Christian G. Zoellin and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Laurent Souef},
title = {{Programmable Deterministic Built-in Self-test}},
booktitle = {Proc. of the International Test Conference (ITC); Santa Clara, CA, USA; October 23-25, 2007},
editor = {International Test Conference},
address = {Washington, D.C.},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {07CH37892C},
pages = {1--9},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2007},
isbn = {978-1-4244-1127-6},
issn = {1089-3539},
doi = {10.1109/TEST.2007.4437611},
keywords = {Deterministic BIST; Test data compression},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {In this paper, we propose a new programmable deterministic Built-In Self-Test
(BIST) method that requires significantly lower storage for deterministic
patterns than existing programmable methods and provides high flexibility for
test engineering in both internal and external test. Theoretical analysis
suggests that significantly more care bits can be encoded in the seed of a
Linear Feedback Shift Register (LFSR), if a limited number of conflicting
equations is ignored in the employed linear equation system. The ignored care
bits are separately embedded into the LFSR pattern. In contrast to known
deterministic BIST schemes based on test set embedding, the embedding logic
function is not hardwired. Instead, this information is stored in memory using
a special compression and decompression method. Experiments for benchmark
circuits and industrial designs demonstrate that the approach has considerably
higher overall coding efficiency than the existing methods.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-79&engl=0}
}
@inproceedings {INPROC-2007-78,
author = {Sybille Hellebrand and Christian G. Zoellin and Hans-Joachim Wunderlich and Stefan Ludwig and Torsten Coym and Bernd Straube},
title = {{A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction}},
booktitle = {Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2885},
pages = {50--58},
type = {Konferenz-Beitrag},
month = {September},
year = {2007},
isbn = {0-7695-2885-6},
issn = {1550-5774},
doi = {10.1109/DFT.2007.43},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/servlet/opac?punumber=4358358},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Decreasing feature sizes have led to an increased vulnerability of random logic
to soft errors. In combinational logic a particle strike may lead to a glitch
at the output of a gate, also referred to as single even transient (SET), which
in turn can propagate to a register and cause a single event upset (SEU) there.
Circuit level modeling and analysis of SETs provides an attractive compromise
between computationally expensive simulations at device level and less accurate
techniques at higher levels. At the circuit level particle strikes crossing a
pn-junction are traditionally modeled with the help of a transient current
source. However, the common models assume a constant voltage across the
pn-junction, which may lead to inaccurate predictions concerning the shape of
expected glitches. To overcome this problem, a refined circuit level model for
strikes through pnjunctions is investigated and validated in this paper. The
refined model yields significantly different results than common models. This
has a considerable impact on SEU prediction, which is confirmed by extensive
simulations at gate level. In most cases, the refined, more realistic, model
reveals an almost doubled risk of a system failure after an SET.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-78&engl=0}
}
@inproceedings {INPROC-2007-77,
author = {Sybille Hellebrand and Christian G. Zoellin and Hans-Joachim Wunderlich and Stefan Ludwig and Torsten Coym and Bernd Straube},
title = {{Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)}},
booktitle = {Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia,September 12-14, 2007},
address = {Ljubljana},
publisher = {MIDEM},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {3--10},
type = {Konferenz-Beitrag},
month = {September},
year = {2007},
isbn = {978-961-91023-7-4},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The increased number of fabrication defects, spatial and temporal variability
of parameters, as well as the growing impact of soft errors in nanoelectronic
systems require a paradigm shift in design, verification and test. A robust
design becomes mandatory to ensure dependable systems and acceptable yields.
Design robustness, however, invalidates many traditional approaches for testing
and implies enormous challenges. The RealTest Project addresses these problems
for nanoscale CMOS and targets unified design and test strategies to support
both a robust design and a coordinated quality assurance after manufacturing
and during the lifetime of a system. The paper first gives a short overview of
the research activities within the project and then focuses on a first result
concerning soft errors in combinational logic. It will be shown that common
electrical models for particle strikes in random logic have underestimated the
effects on the system behavior. The refined model developed within the RealTest
Project predicts about twice as many single events upsets (SEUs) caused by
particle strikes as traditional models.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-77&engl=0}
}
@inproceedings {INPROC-2007-76,
author = {Hans-Joachim Wunderlich and Melani Elm and Stefan Holst},
title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper)}},
booktitle = {Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07); Bled, Slovenia; September 2007},
address = {Ljubljana},
publisher = {MIDEM},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {27--36},
type = {Konferenz-Beitrag},
month = {September},
year = {2007},
isbn = {978-961-91023-7-4},
keywords = {Diagnosis; Debug; Embedded Test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Rising design complexity and shrinking structures pose new challenges for debug
and diagnosis. Finding bugs and defects quickly during the whole life cycle of
a product is crucial for time to market, time to volume and improved product
quality. Debug of design errors and diagnosis of defects have many common
aspects. In this paper we give an overview of state of the art algorithms,
which tackle both tasks, and present an adaptive approach to design debug and
logic diagnosis.
Special design for diagnosis is needed to maintain visibility of internal
states and diagnosability of deeply embedded cores. This article discusses
current approaches to design for diagnosis to support all debug tasks from
first silicon to the system level.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-76&engl=0}
}
@inproceedings {INPROC-2007-33,
author = {Michael Wedel and Peter G{\"o}hner and Jochen G{\"a}ng and Bernd Bertsche and Talal Arnaout and Hans-Joachim Wunderlich},
title = {{Dom{\"a}nen{\"u}bergreifende Zuverl{\"a}ssigkeitsbewertung in fr{\"u}hen Entwicklungsphasen unter Ber{\"u}cksichtigung von Wechselwirkungen}},
booktitle = {5. Paderborner Workshop ``Entwurf mechatronischer Systeme''},
address = {Paderborn},
publisher = {HNI Verlag},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {HNI Verlagsschriftenreihe},
volume = {210},
pages = {257--272},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2007},
keywords = {Zuverl{\"a}ssigkeitsbewertung mechatronischer Systeme; fr{\"u}he Entwicklungsphasen; dom{\"a}nen{\"u}bergreifende Wechselwirkungen; quantitative und qualitative Methoden},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Aufgrund der unvollst{\"a}ndigen Informationen {\"u}ber ein mechatronisches System
stellt die fr{\"u}he Zuverl{\"a}ssigkeitsbewertung eine gro{\ss}e Herausforderung dar.
Um die jeweiligen Vorteile zu nutzen, wurden klassische Ans{\"a}tze in den
einzelnen Dom{\"a}nen kombiniert und in eine ganzheitliche Methode zur
Zuverl{\"a}ssigkeitsbewertung in den fr{\"u}hen Entwicklungsphasen integriert. In
Zusammenarbeit verschiedener Ingenieursdisziplinen wurde die ganzheitliche
Methode um die rechnergest{\"u}tzte Ermittlung von Fehlerzusammenh{\"a}ngen im Rahmen
einer Risikoabsch{\"a}tzung und verschiedene qualitative Modellierungs- und
Analyseans{\"a}tze erweitert. F{\"u}r die systematische Analyse des wechselseitigen
Einflusses der beteiligten Dom{\"a}nen und die Integration in die
Zuverl{\"a}ssigkeitsbewertung wurden Wechselwirkungen zwischen den Dom{\"a}nen
untersucht und klassifiziert.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-33&engl=0}
}
@inproceedings {INPROC-2007-32,
author = {Stefan Holst and Hans-Joachim Wunderlich},
title = {{Adaptive Debug and Diagnosis without Fault Dictionaries}},
booktitle = {12th IEEE European Test Symposium (ETS'07); Freiburg, Germany; May 21-24, 2007},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2827},
pages = {7--12},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2007},
isbn = {0-7695-2827-9},
issn = {1530-1877},
doi = {10.1109/ETS.2007.9},
keywords = {Diagnosis; Debug; Test; VLSI},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.cad.polito.it/~ets08/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Diagnosis is essential in modern chip production to increase yield, and debug
constitutes a major part in the presilicon development process. For recent
process technologies, defect mechanisms are increasingly complex, and
continuous efforts are made to model these defects by using sophisticated fault
models. Traditional static approaches for debug and diagnosis with a simplified
fault model are more and more limited. In this paper, a method is presented,
which identifies possible faulty regions in a combinational circiut, based on
its input/output behavior and independent of a fault model. The new adaptive,
statistical approach combines a flexible and powerful effect-cause pattern
analysis algorithm with high-resolution ATPG. We show the effectiveness of the
approach through experiments with benchmark and industrial circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-32&engl=0}
}
@inproceedings {INPROC-2007-31,
author = {Phillip Oehler and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}},
booktitle = {12th IEEE European Test Symposium (ETS'07); Freiburg, Germany; May 21-24, 2007},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2827},
pages = {91--96},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2007},
isbn = {0-7695-2827-9},
issn = {1530-1877},
doi = {10.1109/ETS.2007.10},
keywords = {Memory repair; BIRA; 2D redundancy},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {An efficient on-chip infrastructure for memory test and repair is crucial to
enhance yield and availability of SoCs. A commonly used repair strategy is to
equip memories with spare rows and columns (2D redundancy). Although exact
algorithms are available for offline repair analysis, they cannot be directly
applied on-chip because of the prohibitive storage requirements for failture
bitmaps and the complex data structures inherent in the algorithms. Existing
heuristics for built-in repair analysis (BIRA) try to circumvent this problem
either by very simple search strategies or by restricting the search to smaller
local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible
repair combination. While a parallel implementation suffers from a high
hardware overhead, a serial implementation leads to high test times. The
integrated built-in test and repair approach proposed in this paper interleaves
test and repair analysis and supports an exact solution without failure bitmap.
The search can be implemented with a stack, which is limited by the number of
redundant elements. The basic search procedure is combined with an efficient
technique to continuously reduce the problem complexity and keep the test and
analysis time low.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-31&engl=0}
}
@inproceedings {INPROC-2007-30,
author = {Phillip Oehler and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair}},
booktitle = {Proceedings 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, Poland, April 2007},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {1--6},
type = {Konferenz-Beitrag},
month = {April},
year = {2007},
isbn = {1-4244-1161-0},
doi = {10.1109/DDECS.2007.4295278},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ui.sav.sk/DDECS2008/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {An efficient on-chip infrastructure for memory test and repair is crucial to
enhance yield and availability of SoCs. A commonly used repair strategy is to
equip memories with spare rows and columns (2D redundancy). To advoid the
prohibitive storage requirements for failure bitmaps and the complex data
structures inherent in most algorithms for offline repair analysis, existing
heuristics for built-in repair analysis (BIRA) either use very simple search
strategies or restict the search to smaller local bitmaps. Exact BIRA
algorithms work with sub analyzers for each possible repair combination. While
a parallel implementation suffers from a high hardware overhead, a serial
implementation leads to increased test times. Recently an integrated built-in
test and repair approach has been proposed which interleaves test and repair
analysis and supports an exact solution with moderate hardware overhead and
reasonable test times. The search is based on a depth first traversal of a
binary tree, which can be efficiently implemented using a stack of limited
size. This algorithm can be realized with different repair strategies guiding
the selection of spare rows or columns in each step. In this paper the impact
of four different repair strategies on the test and repair time is analyzed.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-30&engl=0}
}
@inproceedings {INPROC-2007-25,
author = {Michael E. Imhof and Christian G. Zoellin and Hans-Joachim Wunderlich and Nicolas Maeding and Jens Leenstra},
title = {{Scan Test Planning for Power Reduction}},
booktitle = {44th ACM/IEEE Design Automation Conference (DAC), San Diego, Ca, USA, June 4-8, 2007},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {521--526},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2007},
isbn = {978-1-59593-627-1},
issn = {0738-100X},
doi = {10.1145/1278480.1278614},
keywords = {test planning; power during test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www2.dac.com/44th+dac+_2007_.aspx},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Many STUMPS architectures found in current chip designs allow disabling of
individual scan chains for debug and diagnosis. In a recent paper it has been
shown that this feature can be used for reducing the power consumption during
test. Here, we present an efficient algorithm for the automated generation of a
test plan that keeps fault coverage as well as test time, while significantly
reducing the amount of wasted energy. A fault isolation table, which is usually
used for diagnosis and debug, is employed to accurately determine scan chains
that can be disabled. The algorithm was successfully applied to large
industrial circuits and identifies a very large amount of excess pattern shift
activity.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-25&engl=0}
}
@article {ART-2007-23,
author = {Hans-Joachim Wunderlich and Melani Elm and Stefan Holst},
title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip}},
journal = {Informacije MIDEM; Bled, Slovenia},
address = {Ljubljana},
publisher = {MIDEM},
volume = {37(4},
number = {124)},
pages = {235--243},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {2007},
issn = {0352-9045},
keywords = {Diagnosis; Debug; Embedded Test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Rising design complexity and shrinking structures pose new challenges for debug
and diagnosis. Finding bugs and defects quickly during the whole life cycle of
a product is crucial for time to market, time to volume and improved product
quality. Debug of design errors and diagnosis of defects have many common
aspects. In this paper we give an overview of state of the art algorithms,
which tackle both tasks, and present an adaptive approach to design debug and
logic diagnosis.
Special design for diagnosis is needed to maintain visibility of internal
states and diagnosability of deeply embedded cores. This article discusses
current approaches to design for diagnosis to support all debug tasks from
first silicon to the system level.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-23&engl=0}
}
@article {ART-2007-22,
author = {Sybille Hellebrand and Christian G. Zoellin and Hans-Joachim Wunderlich and Stefan Ludwig and Torsten Coym and Bernd Straube},
title = {{Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)}},
journal = {Informacije MIDEM; Bled, Slovenia},
address = {Ljubljana},
publisher = {MIDEM},
volume = {37(4},
number = {124)},
pages = {212--219},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {2007},
issn = {0352-9045},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The increased number of fabrication defects, spatial and temporal variability
of parameters, as well as the growing impact of soft errors in nanoelectronic
systems require a paradigm shift in design, verification and test. A robust
design becomes mandatory to ensure dependable systems and acceptable yields.
Design robustness, however, invalidates many traditional approaches for testing
and implies enormous challenges. The RealTest Project addresses these problems
for nanoscale CMOS and targets unified design and test strategies to support
both a robust design and a coordinated quality assurance after manufacturing
and during the lifetime of a system. The paper first gives a short overview of
the research activities within the project and then focuses on a first result
concerning soft errors in combinational logic. It will be shown that common
electrical models for particle strikes in random logic have underestimated the
effects on the system behavior. The refined model developed within the RealTest
Project predicts about twice as many single events upsets (SEUs) caused by
particle strikes as traditional models.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-22&engl=0}
}
@article {ART-2007-12,
author = {Frank Novak and Anton Biasizzo and Yves Bertrand and Marie-Lise Flottes and Luz Balado and Joan Figueras and Stefano di Carlo and Paolo Prinetto and Nicoleta Pricopi and Hans-Joachim Wunderlich and Jean Pierre van der Heyden},
title = {{Academic Network for Microelectronic Test Education}},
journal = {The International Journal of Engineering Education},
publisher = {TEMPUS Publications},
volume = {23},
number = {6},
pages = {1245--1253},
type = {Artikel in Zeitschrift},
month = {November},
year = {2007},
issn = {0949-149X},
isbn = {ijee: 2007/00000023/00000006/art00021},
keywords = {microelectronic circuit test; remote on-line test; digital test; mixed-signal test; memory test, automatic test equipment; test education},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.ingentaconnect.com/content/intjee/ijee/2007/00000023/00000006/art00021},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {This paper is an overview of the activities performed in the framework of the
European IST project EuNICE-Test (European Network for Initial and Continuing
Education in VLSI/SOC Testing) using remote automatic test equipment (ATE) ),
addressing the shortage of skills in the microelectronics industry in the field
of electronic testing. The project was based on the experience of the common
test resource centre (CRTC) for French universities. In the framework of the
EuNICE-Test project, the existing network expanded to 4 new academic centres:
Universitat Politecnica de Catalunya, Spain, Politecnico di Torino, Italy,
University of Stuttgart, Germany and Jozef Stefan Institute Ljubljana,
Slovenia. Assessments of the results achieved are presented as well as course
topics and possible future extensions.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-12&engl=0}
}
@article {ART-2007-05,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Juergen Schloeffel and Michael Garbers},
title = {{Deterministic Logic BIST for Transition Fault Testing}},
journal = {IET Computers \& Digital Techniques},
publisher = {Institution of Engineering and Technology},
volume = {1},
number = {3},
pages = {180--186},
type = {Artikel in Zeitschrift},
month = {Mai},
year = {2007},
issn = {1751-8601},
doi = {10.1049/iet-cdt:20060131},
keywords = {Deterministic logic BIST; delay test generation; transition faults},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {BIST is an attractive approach to detect delay faults due to its inherent
support for at-speed test. Deterministic logic BIST (DLBIST) is a technique
which was successfully applied to stuck-at fault testing. As delay faults have
lower random pattern testability than stuck-at faults, the need for DLBIST
schemes is increased. Nevertheless, an extension to delay fault testing is not
trivial, since this necessitates the application of pattern pairs.
Consequently, delay fault testing is expected to require a larger mapping
effort and logic overhead than stuck-at fault testing. In this paper, we
consider the so-called transition fault model, which is widely used for
complexity reasons. We present an extension of a DLBIST scheme for transition
fault testing. Functional justification has been used to generate the required
pattern pairs. The efficiency of the extended scheme is investigated by using
difficult to test industrial designs.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-05&engl=0}
}
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