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@inproceedings {INPROC-2008-95,
author = {Michael E. Imhof and Hans-Joachim Wunderlich and Christian G. Zoellin},
title = {{Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 57), 2. GMM/GI/ITG-Fachtagung; Ingolstadt, Germany, 29.09 - 01.10.2008},
editor = {VDE/VDI and GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {57},
pages = {107--114},
type = {Konferenz-Beitrag},
month = {September},
year = {2008},
isbn = {978-3-8007-3119-0},
issn = {1432-3419},
isbn = {docid: 453119017},
keywords = {Robustes Design; Fehlertoleranz; Verlustleistung; Latch; Register; Single Event Effect},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/453119017.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {F{\"u}r Speicherfelder sind fehlerkorrigiernde Codes die vorherrschende Methode um
akzeptable Fehlerraten zu erreichen. In vielen aktuellen Schaltungen erreicht
die Zahl der Speicherelemente in freier Logik die Gr{\"o}{\ss}enordnung der Zahl von
SRAM-Zellen vor wenigen Jahren. Zur Reduktion der Verlustleistung wird h{\"a}ufig
der Takt der pegelgesteuerten Speicherelemente unterdr{\"u}ckt und die
Speicherlemente m{\"u}ssen ihren Zustand {\"u}ber lange Zeitintervalle halten. Die
Notwendigkeit der Absicherung der Speicherzellen wird zus{\"a}tzlich durch die
Miniaturisierung verst{\"a}rkt, die zu einer erh{\"o}hten Empfindlichkeit der
Speicherelemente gef{\"u}hrt hat.
Dieser Artikel stellt eine Methode zur fehlertoleranten Anordnung von
pegelgesteuerten Speicherelementen vor, die bei unterdr{\"u}cktem Takt
Einfachfehler lokalisieren und Mehrfachfehler detektieren kann. Bei aktiviertem
Takt k{\"o}nnen Einfach- und Mehrfachfehler erkannt werden. Die Register k{\"o}nnen
{\"a}hnlich wie Pr{\"u}fpfade effizient in den Entwurfsgang integriert werden. Die
Diagnoseinformation kann auf Modulebene leicht berechnet und genutzt werden.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-95&engl=0}
}
@inproceedings {INPROC-2008-94,
author = {Michael A. Kochte and Rafal Baranowski and Hans-Joachim Wunderlich},
title = {{Zur Zuverl{\"a}ssigkeitsmodellierung von Hardware-Software-Systemen}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 57), 2. GMM/GI/ITG-Fachtagung; Ingolstadt, Germany, 29.09 - 01.10.2008},
editor = {VDE/VDI and GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {57},
pages = {83--90},
type = {Konferenz-Beitrag},
month = {September},
year = {2008},
isbn = {978-3-8007-3119-0},
issn = {1432-3419},
isbn = {docid: 453119013},
keywords = {Modellierung; Zuverl{\"a}ssigkeit; eingebettete Systeme; System-Level; Systems-on-Chip},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/453119013.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Zur Zuverl{\"a}ssigkeitsanalyse von Hardware-Software-Systemen ist ein Systemmodell
notwendig, welches sowohl Struktur und Architektur der Hardware als auch die
ausgef{\"u}hrte Funktion betrachtet. Wird einer dieser Aspekte des Gesamtsystems
vernachl{\"a}ssigt, kann sich eine zu optimische oder zu konservative Sch{\"a}tzung der
Zuverl{\"a}ssigkeit ergeben.
Ein reines Strukturmodell der Hardware erlaubt, den Einfluss von logischer und
struktureller Fehlermaskierung auf die Fehlerh{\"a}ufigkeit der Hardware zu
bestimmen. Allerdings kann ein solches Modell nicht die Fehlerh{\"a}ufigkeit des
Gesamtsystems hinreichend genau sch{\"a}tzen. Die Ausf{\"u}hrung der Funktion auf dem
System f{\"u}hrt zu speziellen Nutzungs- und Kommunikationsmustern der
Systemkomponenten, die zu erh{\"o}hter oder verminderter Anf{\"a}lligkeit gegen{\"u}ber
Fehlern f{\"u}hren.
Diese Arbeit motiviert die Modellierung funktionaler Aspekte zusammen mit der
Struktur des Systems. Mittels Fehlerinjektion und Simulation wird der starke
Einfluss der Funktion auf die Fehleranf{\"a}lligkeit des Systems aufgezeigt. Die
vorgestellte Methodik, funktionale Aspekte mit in die
Zuverl{\"a}ssigkeitsmodellierung einzubinden, verspricht eine realistischere
Bewertung von Hardware-Software-Systemen},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-94&engl=0}
}
@inproceedings {INPROC-2008-75,
author = {Michael E. Imhof and Hans-Joachim Wunderlich and Christian G. Zoellin},
title = {{Integrating Scan Design and Soft Error Correction in Low-Power Applications}},
booktitle = {Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS'08); Rhodes, Greece, July 7-9, 2008},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3264},
pages = {59--64},
type = {Konferenz-Beitrag},
month = {Juli},
year = {2008},
isbn = {978-0-7695-3264-6},
doi = {10.1109/IOLTS.2008.31},
keywords = {Robust design; fault tolerance; latch; low power; register; single event effects},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Error correcting coding is the dominant technique to achieve acceptable
soft-error rates in memory arrays. In many modern circuits, the number of
memory elements in the random logic is in the order of the number of SRAM cells
on chips only a few years ago. Often latches are clock gated and have to retain
their states during longer periods. Moreover, miniaturization has led to
elevated susceptibility of the memory elements and further increases the need
for protection. This paper presents a fault-tolerant register latch
organization that is able to detect single-bit errors while it is clock gated.
With active clock, single and multiple errors are detected. The registers can
be efficiently integrated similar to the scan design flow, and error detecting
or locating information can be collected at module level. The resulting
structure can be efficiently reused for offline and general online testing.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-75&engl=0}
}
@inproceedings {INPROC-2008-66,
author = {Melanie Elm and Hans-Joachim Wunderlich and Michael E. Imhof and Christian G. Zoellin and Jens Leenstra and Nicolas Maeding},
title = {{Scan Chain Clustering for Test Power Reduction}},
booktitle = {Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008},
address = {New York, NY, USA},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {ACM Order Number},
volume = {477081},
pages = {828--833},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2008},
isbn = {978-1-60558-115-6},
isbn = {ISSN 0738-100X},
doi = {10.1145/1391469.1391680},
keywords = {Test; Design for Test; Low Power; Scan Design},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {An effective technique to save power during scan based test is to switch off
unused scan chains. The results obtained with this method strongly depend on
the mapping of scan flip-flops into scan chains, which determines how many
chains can be deactivated per pattern. In this paper, a new method to cluster
flip-flops into scan chains is presented, which minimizes the power consumption
during test. The approach does not specify any ordering inside the chains and
fits seamlessly to any standard tool for scan chain integration. The
application of known test power reduction techniques to the optimized scan
chain configurations shows significant improvements for large industrial
circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-66&engl=0}
}
@inproceedings {INPROC-2008-65,
author = {Christian G. Zoellin and Hans-Joachim Wunderlich and Ilia Polian and Bernd Becker},
title = {{Selective Hardening in Early Design Steps}},
booktitle = {Proceedings of the 13th IEEE European Test Symposium (ETS'08), Lago Maggiore, Italy, May 25-29, 2008},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {185--190},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2008},
isbn = {978-0-7695-3150-2},
issn = {1530-1877},
doi = {10.1109/ETS.2008.30},
keywords = {Soft error mitigation; reliability},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Hardening a circuit against soft errors should be performed in early design
steps before the circuit is laid out. A viable approach to achieve soft error
rate (SER) reduction at a reasonable cost is to harden only parts of a circuit.
When selecting which locations in the circuit to harden, priority should be
given to critical spots for which an error is likely to cause a system
malfunction. The criticality of the spots depends on parameters not all
available in early design steps. We employ a selection strategy which takes
only gate-level information into account and does not use any low-level
electrical or timing information. We validate the quality of the solution using
an accurate SER estimator based on the new UGC particle strike model. Although
only partial information is utilized for hardening, the exact validation shows
that the susceptibility of a circuit to soft errors is reduced significantly.
The results of the hardening strategy presented are also superior to known
purely topological strategies in terms of both hardware overhead and
protection.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-65&engl=0}
}
@inproceedings {INPROC-2008-36,
author = {Michael A. Kochte and Ramesh Natarajan},
title = {{A framework for scheduling parallel dbms user-defined programs on an attached high-performance computer}},
booktitle = {Proceedings of the 2008 conference on Computing frontiers:CF'08; Ischia, Italy May 5-7, 2008},
publisher = {Association for Computing Machinery, Inc. (ACM)},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {97--104},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2008},
isbn = {978-1-60558-077-7},
doi = {10.1145/1366230.1366245},
keywords = {database accelerators; high-performance computing; parallel user-defined programs},
language = {Englisch},
cr-category = {C.1.4 Processor Architectures, Parallel Architectures},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {We describe a software framework for deploying, scheduling and executing
parallel DBMS user-defined programs on an attached high-performance computer
(HPC) platform. This framework is advantageous for many DBMS workloads in the
following two aspects. First, the long-running user-defined programs can be
speeded up by taking advantage of the greater hardware parallelism available on
the attached HPC platform. Second, the interactive response time of the
remaining applications on the database server platform is improved by the
off-loading of long-running user-defined programs to the attached HPC platform.
Our framework provides a new approach for integrating high-performance
computing into the workflow of query-oriented, computationally-intensive
applications.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-36&engl=0}
}
@inproceedings {INPROC-2008-35,
author = {Uranmandakh Amgalan and Christian Hachmann and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Signature Rollback – A Technique for Testing Robust Circuits}},
booktitle = {Proceedings of the 26th IEEE VLSI Test Symposium (VTS'08); San Diego, California, USA; Apr 27th - May 1st, 2008},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3123},
pages = {125--130},
type = {Konferenz-Beitrag},
month = {April},
year = {2008},
isbn = {978-0-7695-3123-6},
issn = {1093-0167},
doi = {10.1109/VTS.2008.34},
keywords = {Embedded Test; Robust Design; Rollback and Recovery; Test Quality and Reliability; Time Redundancy},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Dealing with static and dynamic parameter variations has become a major
challenge for design and test. To avoid unnecessary yield loss and to ensure
reliable system operation a robust design has become mandatory. However,
standard structural test procedures still address classical fault models and
cannot deal with the non-deterministic behavior caused by parameter variations
and other reasons. Chips may be rejected, even if the test reveals only
non-critical failures that could be compensated during system operation. This
paper introduces a scheme for embedded test, which can distinguish critical
permanent and noncritical transient failures for circuits with time redundancy.
To minimize both yield loss and the overall test time, the scheme relies on
partitioning the test into shorter sessions. If a faulty signature is observed
at the end of a session, a rollback is triggered, and this particular session
is repeated. An analytical model for the expected overall test time provides
guidelines to determine the optimal parameters of the scheme.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-35&engl=0}
}
@inproceedings {INPROC-2008-24,
author = {Melanie Elm and Hans-Joachim Wunderlich},
title = {{Scan Chain Organization for Embedded Diagnosis}},
booktitle = {Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {CFP08162-DVD},
pages = {468--473},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2008},
isbn = {978-3-9810801-3-1},
doi = {10.1109/DATE.2008.4484725},
keywords = {design for diagnosis; embedded test; scan design},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Keeping diagnostic resolution as high as possible while maximizing the
compaction ratio is subject to research since the advent of embedded test. In
this paper, we present a novel scan design methodology to maximize diagnostic
resolution when compaction is employed. The essential idea is to consider the
diagnostic resolution during the clustering of scan elements to scan chains.
Our methodology does not depend on a fault model and is helpful with any type
of compactor.
A linear time heuristic is presented to solve the scan chain clustering
problem. We evaluate our approach for industrial and academic benchmark
circuits. It turns out to be superior to both random and to layout driven scan
chain clustering. The methodology is applicable to any gate-level design and
fits smoothly into an industrial design flow.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-24&engl=0}
}
@inproceedings {INPROC-2008-22,
author = {Michael A. Kochte and Christian G. Zoellin and Michael E. Imhof and Hans-Joachim Wunderlich},
title = {{Test Set Stripping Limiting the Maximum Number of Specified Bits}},
booktitle = {Proc. of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08); Hong Kong, SAR, China, 23-25 January 2008,},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3110},
pages = {581--586},
type = {Konferenz-Beitrag},
month = {Januar},
year = {2008},
isbn = {978-0-7695-3110-6},
doi = {10.1109/DELTA.2008.64},
keywords = {test relaxation; test generation; tailored ATPG},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.ece.ust.hk/delta2008/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {This paper presents a technique that limits the maximum number of specified
bits of any pattern in a given test set. The outlined method uses algorithms
similar to ATPG, but exploits the information in the test set to quickly find
test patterns with the desired properties. The resulting test sets show a
significant reduction in the maximum number of specified bits in the test
patterns. Furthermore, results for commercial ATPG test sets show that even the
overall number of specified bits is reduced substantially},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-22&engl=0}
}
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