@inproceedings {INPROC-2009-59,
    author = {Abdul-Wahid Hakmi and Stefan Holst and Hans-Joachim Wunderlich and Juergen Schloeffel and Friedrich Hapke and Andreas Glowatz},
    title = {{Restrict Encoding for Mixed-Mode BIST}},
    booktitle = {27th IEEE VLSI Test Symposium (VTS'09); Santa Cruz, California, USA; May 3-7, 2009},
    editor = {IEEE Computer Society},
    address = {Los Alamitos, California},
    publisher = {IEEE Computer Society Conference Publishing Services},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Computer Society Order Number},
    volume = {P3598},
    pages = {179--184},
    type = {Konferenz-Beitrag},
    month = {Mai},
    year = {2009},
    isbn = {978-0-7695-3598-2},
    issn = {1093-0167},
    doi = {10.1109/VTS.2009.43},
    keywords = {Deterministic BIST},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and
      deterministic test. This paper presents a synthesis technique for a mixed-mode
      BIST scheme which is able to exploit the regularities of a deterministic test
      pattern set for minimizing the hardware overhead and memory requirements. The
      scheme saves more than 50\% hardware costs compared with the best schemes known
      so far while complete programmability is still preserved.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-59&engl=0}
 }

@inproceedings {INPROC-2009-58,
    author = {Stefan Holst and Hans-Joachim Wunderlich},
    title = {{A diagnosis algorithm for extreme space compaction}},
    booktitle = {Design, Automation and Test in Europe (DATE'09); Nice; France; April 20-24, 2009},
    editor = {European Design and Automation Association},
    publisher = {IEEE Xplore},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Catalog Number},
    volume = {CFP09162-DVD},
    pages = {1355--1360},
    type = {Konferenz-Beitrag},
    month = {April},
    year = {2009},
    isbn = {978-1-4244-3781-8},
    issn = {1530-1591},
    isbn = {ieee: 5090875},
    keywords = {Compaction; Design-for-test; Diagnosis; Embedded diagnosis; Multi-site test},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090875},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {During volume testing, test application time, test data volume and high
      performance automatic test equipment (ATE) are the major cost factors. Embedded
      testing including built-in self-test (BIST) and multi-site testing are quite
      effective cost reduction techniques which may make diagnosis more complex. This
      paper presents a test response compaction scheme and a corresponding diagnosis
      algorithm which are especially suited for BIST and multi-site testing. The
      experimental results on industrial designs show, that test time and response
      data volume reduces significantly and the diagnostic resolution even improves
      with this scheme. A comparison with X-Compact shows, that simple parity
      information provides higher diagnostic resolution per response data bit than
      more complex signatures.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-58&engl=0}
 }

@inproceedings {INPROC-2009-57,
    author = {Michael A. Kochte and Christian G. Zoellin and Michael E. Imhof and Rauf Salimi Khaligh and Martin Radetzki and Hans-Joachim Wunderlich and Stefano Di Carlo and Prinetto Paolo},
    title = {{Test Exploration and Validation Using Transaction Level Models}},
    booktitle = {Design, Automation and Test in Europe (DATE'09); Nice; France; April 20-24, 2009},
    editor = {European Design and Automation Association},
    publisher = {IEEE Xplore},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Catalog Number},
    volume = {CFP09162-DVD},
    pages = {1250--1253},
    type = {Konferenz-Beitrag},
    month = {April},
    year = {2009},
    isbn = {978-1-4244-3781-8},
    issn = {1530-1591},
    isbn = {ieee: 5090856},
    keywords = {Test of systems-on-chip; design-for-test, transaction level modeling},
    language = {Deutsch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090856},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {The complexity of the test infrastructure and test strategies in
      systems-on-chip approaches the complexity of the functional design space. This
      paper presents test design space exploration and validation of test strategies
      and schedules using transaction level models (TLMs). All aspects of the test
      infrastructure such as test access mechanisms, test wrappers, test data
      compression and test controllers are modeled at transaction level. Since many
      aspects of testing involve the transfer of a significant amount of test stimuli
      and responses, the communication-centric view of TLMs suits this purpose
      exceptionally well. A case study shows how TLMs can be used to efficiently
      evaluate DfT decisions in early design steps and how to evaluate test
      scheduling and resource partitioning during test planning. The presented
      approach has significantly higher simulation efficiency than RTL and gate level
      approaches.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-57&engl=0}
 }

@inproceedings {INPROC-2009-56,
    author = {Michael A. Kochte and Christian G. Zoellin and Michael E. Imhof and Rauf Salimi Khaligh and Martin Radetzki and Hans-Joachim Wunderlich and Stefano Di Carlo and Prinetto Paolo},
    title = {{Test Exploration and Validation Using Transaction Level Models}},
    booktitle = {Design, Automation and Test in Europe (DATE'09); Nice; France; April 20-24, 2009},
    editor = {European Design and Automation Association},
    publisher = {IEEE Xplore},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    pages = {1250--1253},
    type = {Konferenz-Beitrag},
    month = {April},
    year = {2009},
    isbn = {978-1-4244-3781-8},
    issn = {1530-1591},
    keywords = {Test of systems-on-chip; design-for-test; transaction level modeling},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {The complexity of the test infrastructure and test strategies in
      systems-on-chip approaches the complexity of the functional design space. This
      paper presents test design space exploration and validation of test strategies
      and schedules using transaction level models (TLMs). All aspects of the test
      infrastructure such as test access mechanisms, test wrappers, test data
      compression and test controllers are modeled at transaction level. Since many
      aspects of testing involve the transfer of a significant amount of test stimuli
      and responses, the communication-centric view of TLMs suits this purpose
      exceptionally well. A case study shows how TLMs can be used to efficiently
      evaluate DfT decisions in early design steps and how to evaluate test
      scheduling and resource partitioning during test planning. The presented
      approach has significantly higher simulation efficiency than RTL and gate level
      approaches.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-56&engl=0}
 }

@inproceedings {INPROC-2009-106,
    author = {Melanie Elm and Hans-Joachim Wunderlich},
    title = {{XP-SISR: Eingebaute Selbstdiagnose f{\"u}r Schaltungen mit Pr{\"u}fpfad}},
    booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 61), 3. GMM/GI/ITG-Fachtagung; Stuttgart, Germany, 21.09 - 23.09.2009},
    editor = {GMM/VDE/VDI/ITG},
    address = {Berlin},
    publisher = {VDE Verlag GmbH},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {GMM-Fachbericht},
    volume = {61},
    pages = {21--28},
    type = {Konferenz-Beitrag},
    month = {September},
    year = {2009},
    isbn = {978-3-8007-3178-7},
    issn = {1432-341},
    isbn = {docid: 453178004},
    keywords = {Logic BIST; Diagnosis},
    language = {Deutsch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    ee = {http://www.vde-verlag.de/proceedings-de/453178004.html},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Die Vorteile des Eingebauten Selbsttests (BIST - Built-In Self-Test) sind
      bekannt, f{\"u}r eingebettete Speicher ist BIST sogar die bevorzugte Teststrategie.
      F{\"u}r freie Logik wird BIST deutlich seltener eingesetzt. Grund hierf{\"u}r ist zum
      einen, dass deterministische Testmuster f{\"u}r eine hohe Fehlerabdeckung ben{\"o}tigt
      werden und diese im Selbsttest hohe Kosten verursachen. Zum anderen lassen sich
      aus den Testantworten, die zu einer einzigen Signatur kompaktiert werden, nur
      wenige diagnostische Informationen ziehen. In den vergangenen Jahren wurden
      kontinuierlich Fortschritte zur L{\"o}sung des ersten Problems erzielt. Dieser
      Beitrag befasst sich mit der L{\"o}sung des zweiten Problems. Eine neue Methode f{\"u}r
      die Eingebaute Selbstdiagnose (BISD - Built-In Self-Diagnosis) wird
      vorgeschlagen. Kern der Methode ist eine kombinierte, extreme Raum- und
      Zeitkompaktierung, die es erstmals erm{\"o}glicht, erwartete Antworten und
      fehlerhafte Antworten mit vernachl{\"a}ssigbarem Aufwand auf dem zu testenden Chip
      zu speichern. Somit k{\"o}nnen in einer einzigen Selbsttestsitzung pro Chip alle
      zur Diagnose notwendigen Daten gesammelt werden. Das BISD Schema umfasst neben
      der Kompaktierungshardware einen Diagnosealgorithmus und ein Verfahren zur
      Testmustererzeugung, die Aliasingeffekte und die durch die starke Kompaktierung
      verringerte diagnostische Aufl{\"o}sung kompensieren k{\"o}nnen. Experimente mit
      aktuellen, industriellen Schaltungen zeigen, dass die diagnostische Aufl{\"o}sung
      im Vergleich zum externen Test erhalten bleibt und der zus{\"a}tzliche
      Hardware-Aufwand zu vernachl{\"a}ssigen ist.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-106&engl=0}
 }

@inproceedings {INPROC-2009-105,
    author = {Michael A. Kochte and Stefan Holst and Melanie Elm and Hans-Joachim Wunderlich},
    title = {{Test Encoding for Extreme Response Compaction}},
    booktitle = {14th IEEE European Test Symposium (ETS'09); Sevilla, Spain; May 25-29, 2009},
    editor = {IEEE Computer Society},
    address = {Los Alamitos, California},
    publisher = {IEEE Computer Society Conference Publishing Services},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Computer Society Order Number},
    volume = {P3703},
    pages = {155--160},
    type = {Konferenz-Beitrag},
    month = {Mai},
    year = {2009},
    isbn = {978-0-7695-3703-0},
    issn = {1530-1877},
    doi = {10.1109/ETS.2009.22},
    keywords = {Design for Test; Embedded Diagnosis; Response Compaction; Test Compression},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Optimizing bandwidth by compression and compaction always has to solve the
      trade-off between input bandwidth reduction and output bandwidth reduction.
      Recently it has been shown that splitting scan chains into shorter segments and
      compacting the shift data outputs into a singleparity bit reduces the test
      response data to one bit per cycle without affecting fault coverage and
      diagnostic resolution if the compactor's structure is included into the ATPG
      process.This test data reduction at the output side comes with challenges at
      the input side. The bandwidth requirement grows due to the increased number of
      chains and due to a drastically decreased amount of don't care values in the
      test patterns. The paper at hand presents a new iterative approach to test set
      encoding which optimizes bandwidth on both input and output side while keeping
      the diagnostic resolution and fault coverage. Experiments with industrial
      designs demonstrate that test application time, test data volume and diagnostic
      resolution are improved at the same time and for most designs testing with a
      bandwidth of three bits per cycle is possible.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-105&engl=0}
 }

@inproceedings {INPROC-2009-104,
    author = {Michael A. Kochte and Christian G. Zoellin and Hans-Joachim Wunderlich},
    title = {{Concurrent Self-Test with Partially Speci\&\#64257;ed Patterns For Low Test Latency and Overhead}},
    booktitle = {14th IEEE European Test Symposium (ETS'09); Sevilla, Spain; May 25-29, 2009},
    editor = {IEEE Computer Society},
    address = {Los Alamitos, California},
    publisher = {IEEE Computer Society Conference Publishing Services},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Computer Society Order Number},
    volume = {P3703},
    pages = {53--58},
    type = {Konferenz-Beitrag},
    month = {Mai},
    year = {2009},
    isbn = {978-0-7695-3703-0},
    issn = {1530-1877},
    doi = {10.1109/ETS.2009.26},
    keywords = {BIST; Concurrent self test; test generation},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Structural on-line self-test may be performed to detect permanent faults and
      avoid their accumulation. This paper improves concurrent BIST techniques based
      on a deterministic test set. Here, the test patterns are specially generated
      with a small number of specified bits. This results in very low test latency,
      which reduces the likelihood of fault accumulation. Experiments with a large
      number of circuits show that the hardware overhead is significantly lower than
      the overhead for previously published methods. Furthermore, the method allows
      to tradeoff fault coverage, test latency and hardware overhead.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-104&engl=0}
 }

@article {ART-2009-23,
    author = {Stefan Holst and Hans-Joachim Wunderlich},
    title = {{Adaptive Debug and Diagnosis Without Fault Dictionaries}},
    journal = {Journal of Electronic Testing - Theory and Applications (JETTA); August 2009},
    publisher = {Springer Netherlands},
    volume = {25},
    number = {4-5},
    pages = {259--268},
    type = {Artikel in Zeitschrift},
    month = {August},
    year = {2009},
    issn = {0923-8174},
    doi = {10.1007/s10836-009-5109-3},
    keywords = {Diagnosis; Debug; Test; VLSI},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Diagnosis is essential in modern chip production to increase yield, and debug
      constitutes a major part in the pre-silicon development process. For recent
      process technologies, defect mechanisms are increasingly complex, and
      continuous efforts are made to model these defects by using sophisticated fault
      models. Traditional static approaches for debug and diagnosis with a simplified
      fault model are more and more limited. In this paper, a method is presented,
      which identifies possible faulty regions in a combinational circuit, based on
      its input/output behavior and independent of a fault model. The new adaptive,
      statistical approach is named POINTER for 'Partially Overlapping Impact
      couNTER' and combines a flexible and powerful effect-cause pattern analysis
      algorithm with high-resolution ATPG. We show the effectiveness of the approach
      through experiments with benchmark and industrial circuits. In addition, even
      without additional patterns this analysis method provides good resolution for
      volume diagnosis, too.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2009-23&engl=0}
 }

@inbook {INBOOK-2009-12,
    author = {Christian G. Zoellin and Hans-Joachim Wunderlich},
    title = {{Power-Aware Design-for-Test}},
    series = {Power-Aware Testing and Test Strategies for Low Power Devices},
    publisher = {Springer Berlin Heidelberg},
    pages = {117--146},
    type = {Beitrag in Buch},
    month = {Dezember},
    year = {2009},
    isbn = {978-1-4419-0927-5},
    doi = {10.1007/978-1-4419-0928-2_4},
    language = {Englisch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {This chapter describes Design-for-Test (DfT) techniques that allow for
      controlling the power consumption and reduce the overall energy consumed during
      a test. While some of the techniques described elsewhere in this book may also
      involve special DfT, the topics discussed here are orthogonal to those
      techniques and may be implemented independently.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-12&engl=0}
 }

@inbook {INBOOK-2009-11,
    author = {Hans-Joachim Wunderlich and Stefan Holst},
    title = {{Generalized Fault Modeling for Logic Diagnosis}},
    series = {Models in Hardware Testing},
    publisher = {Springer Berlin Heidelberg},
    series = {Frontiers in Electronic Testing},
    volume = {43},
    pages = {133--155},
    type = {Beitrag in Buch},
    month = {November},
    year = {2009},
    isbn = {978-90-481-3281-2},
    issn = {0929-1296},
    doi = {10.1007/978-90-481-3282-9_5},
    language = {Englisch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    contact = {Prof. Dr. Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {To cope with the numerous defect mechanisms in nanoelectronic technology, more
      and more complex fault models have been introduced. Each model comes with its
      own properties and algorithms for test generation and logic diagnosis. In
      diagnosis, however, the defect mechanisms of a failing device are not known in
      advance, and algorithms that assume a specific fault model may fail. Therefore,
      diagnosis techniques have been proposed that relax fault assumptions or even
      work without any fault model. In this chapter, we establish a generalized fault
      modeling technique and notation. Based on this notation, we describe and
      classify existing models and investigate the properties of a fault model
      independent diagnosis technique.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-11&engl=0}
 }

@inbook {INBOOK-2009-10,
    author = {Patrick Girard and Hans-Joachim Wunderlich},
    title = {{Models for Power-Aware Testing}},
    series = {Models in Hardware Testing},
    publisher = {Springer Berlin Heidelberg},
    series = {Frontiers in Electronic Testing},
    volume = {43},
    pages = {187--215},
    type = {Beitrag in Buch},
    month = {November},
    year = {2009},
    isbn = {978-90-481-3281-2},
    issn = {0929-1296},
    doi = {10.1007/978-90-481-3282-9_7},
    language = {Englisch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    contact = {Prof. Dr. Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Power consumption of circuits and systems receives more and more attention. In
      test mode, power consumption is even more critical than in system model and has
      severe impact on reliability, yield and test costs. This chapter describes the
      different types and sources of test power. Power-aware techniques for test
      pattern generation, design for test and test data compression are presented
      which allow efficient power constrained testing with minimized hardware cost
      and test application time.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-10&engl=0}
 }

@inbook {INBOOK-2009-09,
    author = {Hans-Joachim Wunderlich and Melanie Elm and Michael Kochte},
    title = {{Bewertung und Verbesserung der Zuverl{\"a}ssigkeit von mikroelektronischen Komponenten in mechatronischen Systemen}},
    series = {Zuverl{\"a}ssigkeit mechatronischer Systeme - Grundlagen und Bewertung in fr{\"u}hen Entwicklungsphasen},
    address = {Berlin Heidelberg},
    publisher = {Springer Berlin Heidelberg},
    series = {VDI-Buch},
    pages = {391--464},
    type = {Beitrag in Buch},
    month = {Februar},
    year = {2009},
    isbn = {978-3-540-85089-2},
    doi = {10.1007/978-3-540-85091-5},
    language = {Deutsch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    contact = {Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {In den letzten Jahrzehnten hat der Anteil der informationsverarbeitenden
      Komponenten an den Herstellungskosten mechatronischer Systeme rapide
      zugenommen. In den 70er Jahren machte die Informationsverarbeitung noch ca. 15\%
      des Systems aus. Zu Beginn dieses Jahrtausends sind es bereits {\"u}ber 60\% [8.9],
      wie auch aus Abb. 8.1 hervorgeht. Dieser Zuwachs in den Herstellungskosten ist
      auf die Zunahme der durch die Informationsverarbeitung realisierten Funktionen
      zur{\"u}ckzuf{\"u}hren. Sehr deutlich ist diese Zunahme im Automobil zu beobachten.
      W{\"a}hrend das Antiblockiersystem und die digitale Motorsteuerung schon seit
      Jahren zum Standard geh{\"o}ren, werden nun zunehmend auch Fahrerassistenz- und
      Infotainmentsysteme ins Kraftfahrzeug integriert. Bei diesen Systemen beginnt
      die Grenze zwischen klassischer Sicherheits- und Komfortfunktion zu
      verschwimmen. Die Bandbreite m{\"o}glichen Fehlverhaltens reicht vom Ausfall des
      Navigationssystems {\"u}ber St{\"o}rungen der Zentralverriegelung bis hin zum
      automatischen Einleiten von Bremsman{\"o}vern bei hohen Geschwindigkeiten.
      Entsprechend ergeben sich hier hohe Anforderungen an die Zuverl{\"a}ssigkeit dieser
      Systeme.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-09&engl=0}
 }

@book {BOOK-2009-04,
    editor = {Bernd Bertsche and Peter G{\"o}hner and Uwe Jensen and Wolfgang Schink{\"o}the and Hans-Joachim Wunderlich},
    title = {{Zuverl{\"a}ssigkeit mechatronischer Systeme}},
    publisher = {Springer Berlin Heidelberg},
    series = {VDI-Buch},
    pages = {464},
    type = {Buch},
    month = {Februar},
    year = {2009},
    isbn = {978-3-540-85089-2},
    doi = {10.1007/978-3-540-85091-5},
    language = {Deutsch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=BOOK-2009-04&engl=0}
 }

@book {BOOK-2009-03,
    editor = {Hans-Joachim Wunderlich},
    title = {{Models in Hardware Testing}},
    publisher = {Springer Berlin Heidelberg},
    series = {Frontiers in Electronic Testing},
    volume = {43},
    pages = {257},
    type = {Buch},
    month = {November},
    year = {2009},
    isbn = {978-90-481-3281-2},
    issn = {978-90-481-3281-2},
    doi = {10.1007/978-90-481-3282-9},
    language = {Englisch},
    cr-category = {B.8.2 Performance Analysis and Design Aids},
    contact = {Prof. Dr. Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=BOOK-2009-03&engl=0}
 }