@inproceedings {INPROC-2010-91,
    author = {Michael A. Kochte and Marcel Schaal and Hans-Joachim Wunderlich and Christian G. Zoellin},
    title = {{Efficient Fault Simulation on Many-Core Processors}},
    booktitle = {Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 13 - 18, 2010},
    address = {New York, NY, USA},
    publisher = {Association for Computing Machinery},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {ACM Order Number},
    volume = {4770101},
    pages = {380--385},
    type = {Konferenz-Beitrag},
    month = {Juni},
    year = {2010},
    isbn = {978-1-4503-0002-5},
    issn = {0738-100X},
    doi = {10.1145/1837274.1837369},
    keywords = {Parallel Fault Simulation; Many-Core Processors; PPSFP},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    ee = {http://doi.acm.org/10.1145/1837274.1837369},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Fault simulation is essential in test generation, design for test and
      reliability assessment of integrated circuits. Reliability analysis and the
      simulation of self-test structures are particularly computationally expensive
      as a large number of patterns has to be evaluated. In this work, we propose to
      map a fault simulation algorithm based on the parallel-pattern single-fault
      propagation (PPSFP) paradigm to many-core architectures and describe the
      involved algorithmic optimizations. Many-core architectures are characterized
      by a high number of simple execution units with small local memory. The
      proposed fault simulation algorithm exploits the parallelism of these
      architectures by use of parallel data structures. The algorithm is implemented
      for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a
      speed-up of up to 17x compared to an existing GPU fault-simulation algorithm
      and up to 16x compared to state-of-the-art algorithms on conventional processor
      architectures.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-91&engl=0}
 }

@inproceedings {INPROC-2010-90,
    author = {Michael A. Kochte and Christian G. Zoellin and Rafal Baranowski and Michael E. Imhof and Hans-Joachim Wunderlich and Nadereh Hatami and Stefano Di Carlo and Paolo Prinetto},
    title = {{Effiziente Simulation von strukturellen Fehlern f{\"u}r die Zuverl{\"a}ssigkeitsanalyse auf Systemebene}},
    booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 66), 4. GMM/GI/ITG-Fachtagung; Wildbad Kreuth, Germany, September 13-15, 2010},
    editor = {GMM},
    address = {Berlin},
    publisher = {VDE Verlag GmbH},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {GMM-Fachbericht},
    volume = {66},
    pages = {25--32},
    type = {Konferenz-Beitrag},
    month = {September},
    year = {2010},
    isbn = {978-3-8007-3299-9},
    language = {Deutsch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    ee = {http://www.vde-verlag.de/proceedings-de/453299003.html},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {In aktueller Prozesstechnologie muss die Zuverl{\"a}ssigkeit in allen
      Entwurfsschritten von eingebetteten Systemen betrachtet werden. Methoden, die
      nur Modelle auf unteren Abstraktionsebenen, wie Gatter- oder
      Registertransferebene, verwenden, bieten zwar eine hohe Genauigkeit, sind aber
      zu ineffizient, um komplexe Hardware/Software-Systeme zu analysieren. Hier
      werden ebenen{\"u}bergreifende Verfahren ben{\"o}tigt, die auch hohe Abstraktion
      unterst{\"u}tzen, um effizient die Auswirkungen von Defekten im System bewerten zu
      k{\"o}nnen. Diese Arbeit stellt eine Methode vor, die aktuelle Techniken f{\"u}r die
      effiziente Simulation von strukturellen Fehlern mit Systemmodellierung auf
      Transaktionsebene kombiniert. Auf dieseWeise ist es m{\"o}glich, eine pr{\"a}zise
      Bewertung der Fehlerauswirkung auf das gesamte Hardware/Software-System
      durchzuf{\"u}hren. Die Ergebnisse einer Fallstudie eines Hardware/Software-Systems
      zur Datenverschl{\"u}sselung und Bildkompression werden diskutiert und die Methode
      wird mit einem Standard-Fehlerinjektionsverfahren verglichen.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-90&engl=0}
 }

@inproceedings {INPROC-2010-88,
    author = {B. Becker and S. Hellebrand and I. Polian and B. Straube and W. Vermeiren and H.-J. Wunderlich},
    title = {{Massive statistical process variations: A grand challenge for testing nanoelectronic circuits}},
    booktitle = {4th Workshop on Dependable and Secure Nanocomputing (WDSN10), Chicago, IL, USA, June 28 - July 01, 2010},
    editor = {IFIP IEEE Computer Society},
    publisher = {IEEE Xplore},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Catalog Number},
    volume = {FP1041K-ART},
    pages = {95--100},
    type = {Konferenz-Beitrag},
    month = {Juni},
    year = {2010},
    isbn = {978-1-4244-7729-6},
    doi = {10.1109/DSNW.2010.5542612},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Increasing parameter variations, high defect densities and a growing
      susceptibility to external noise in nanoscale technologies have led to a
      paradigm shift in design. Classical design strategies based on worst-case or
      average assumptions have been replaced by statistical design, and new robust
      and variation tolerant architectures have been developed. At the same time
      testing has become extremely challenging, as parameter variations may lead to
      an unacceptable behavior or change the impact of defects. Furthermore, for
      robust designs a precise quality assessment is required particularly showing
      the remaining robustness in the presence of manufacturing defects. The paper
      pinpoints the key challenges for testing nanoelectronic circuits in more
      detail, covering the range of variation-aware fault modeling via methods for
      statistical testing and their algorithmic foundations to robustness analysis
      and quality binning.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-88&engl=0}
 }

@inproceedings {INPROC-2010-70,
    author = {Claus Braun and Hans-Joachim Wunderlich},
    title = {{Algorithm-based fault tolerance for many-core architectures}},
    booktitle = {15th IEEE European Test Symposium (ETS'10); Praha, Czech Republic; May 24 - 28, 2010},
    editor = {IEEE Computer Society},
    address = {Los Alamitos, California},
    publisher = {IEEE Computer Society Conference Publishing Services},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Catalog Number},
    volume = {CFP10216-USB},
    pages = {253--253},
    type = {Konferenz-Beitrag},
    month = {Mai},
    year = {2010},
    isbn = {978-1-4244-5833-2},
    issn = {1530-1877},
    doi = {10.1109/ETSYM.2010.5512738},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
                   C.1.4 Processor Architectures, Parallel Architectures,
                   C.4 Performance of Systems,
                   D.1.3 Concurrent Programming},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Modern many-core architectures with hundreds of cores provide a high
      computational potential. This makes them particularly interesting for
      scientific high-performance computing and simulation technology. Like all nano
      scaled semiconductor devices, many-core processors are prone to reliability
      harming factors like variations and soft errors. One way to improve the
      reliability of such systems is software-based hardware fault tolerance. Here,
      the software is able to detect and correct errors introduced by the hardware.
      In this work, we propose a software-based approach to improve the reliability
      of matrix operations on many-core processors. These operations are key
      components in many scientific applications.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-70&engl=0}
 }

@inproceedings {INPROC-2010-62,
    author = {Christian G. Zoellin and Hans-Joachim Wunderlich},
    title = {{Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes}},
    booktitle = {IEEE VLSI Test Conference (VTS); Santa Cruz, CA, USA; April 18 - 21, 2010},
    editor = {IEEE Computer Society},
    publisher = {IEEE Computer Society},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    series = {IEEE Catalog Number},
    volume = {CFP10029-CDR},
    pages = {380--385},
    type = {Konferenz-Beitrag},
    month = {April},
    year = {2010},
    isbn = {978-1-4244-6648-1},
    issn = {1093-0167},
    doi = {10.1109/VTS.2010.5469607},
    keywords = {Delay test; power-aware testing; built-in self-test},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {High delay-fault coverage requires rather sophisticated clocking schemes in
      test mode, which usually combine launch-on-shift and launch-on-capture
      strategies. These complex clocking schemes make low power test planning more
      difficult as initialization, justification and propagation require multiple
      clock cycles. This paper describes a unified method to map the sequential test
      planning problem to a combinational circuit representation. The combinational
      representation is subject to known algorithms for efficient low power built-in
      self-test planning. Experimental results for a set of industrial circuits show
      that even rather complex test clocking schemes lead to an efficient low power
      test plan.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-62&engl=0}
 }

@inproceedings {INPROC-2010-34,
    author = {Melanie Elm and Hans-Joachim Wunderlich},
    title = {{BISD: Scan-Based Built-In Self-Diagnosis}},
    booktitle = {ACM/IEEE Design Automation and Test in Europe (DATE'10); Dresden, Germany; March 8-12, 2010},
    editor = {European Design and Automation Association},
    publisher = {IEEE Xplore},
    institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
    pages = {1243--1248},
    type = {Konferenz-Beitrag},
    month = {M{\"a}rz},
    year = {2010},
    isbn = {978-3-9810801-6-2},
    keywords = {Logic BIST, Diagnosis},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5456997},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Built-In Self-Test (BIST) is less often applied to random logic than to
      embedded memories due to the following reasons: Firstly, for a satisfiable
      fault coverage it may be necessary to apply additional deterministic patterns,
      which cause additional hardware costs. Secondly, the BIST-signature reveals
      only poor diagnostic information. Recently, the first issue has been addressed
      successfully. The paper at hand proposes a viable, effective and cost efficient
      solution for the second problem. The paper presents a new method for Built-In
      Self-Diagnosis (BISD). The core of the method is an extreme response compaction
      architecture, which for the first time enables an autonomous on-chip evaluation
      of test responses with negligible hardware overhead. The key advantage of this
      architecture is that all data, which is relevant for a subsequent diagnosis, is
      gathered during just one test session. The BISD method comprises a hardware
      scheme, a test pattern generation approach and a diagnosis algorithm.
      Experiments conducted with industrial designs substantiate that the additional
      hardware overhead introduced by the BISD method is on average about 15\% of the
      BIST area, and the same diagnostic resolution can be obtained as for external
      testing.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-34&engl=0}
 }

@article {ART-2010-12,
    author = {Michael A. Kochte and Christian G. Zoellin and Hans-Joachim Wunderlich},
    title = {{Efficient Concurrent Self-Test with Partially Specified Patterns}},
    journal = {Journal of Electronic Testing: Theory and Applications (JETTA), 2010},
    publisher = {Springer Netherlands},
    volume = {26},
    type = {Artikel in Zeitschrift},
    month = {August},
    year = {2010},
    isbn = {0923-8174},
    doi = {10.1007/s10836-010-5167-6},
    keywords = {Concurrent self-test; BIST; Test generation; VLSI},
    language = {Englisch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Structural on-line self-test may be performed to detect permanent faults and
      avoid their accumulation in the system. This paper improves existing techniques
      for concurrent BIST that are based on a deterministic test set. Here, the test
      patterns are specially generated with a small number of specified bits. This
      results in very low test length and fault detection latency, which allows to
      frequently test critical faults. As a consequence, the likelihood of fault
      accumulation is reduced. Experiments with benchmark circuits show that the
      hardware overhead is significantly lower than the overhead of the state of the
      art. Moreover, a case-study on a super-scalar RISC processor demonstrates the
      feasibility of the method.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2010-12&engl=0}
 }

@article {ART-2010-11,
    author = {Claus Braun and Hans-Joachim Wunderlich},
    title = {{Algorithmen-basierte Fehlertoleranz f{\"u}r Many-Core-Architekturen}},
    journal = {it - Information Technology},
    publisher = {Oldenbourg Wissenschaftsverlag},
    volume = {52},
    number = {4},
    pages = {209--215},
    type = {Artikel in Zeitschrift},
    month = {August},
    year = {2010},
    issn = {1611-2776},
    doi = {10.1524/itit.2010.0593},
    keywords = {Zuverl{\"a}ssigkeit; Fehlertoleranz; parallele Architekturen; parallele Programmierung},
    language = {Deutsch},
    cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
                   C.1.4 Processor Architectures, Parallel Architectures,
                   C.4 Performance of Systems,
                   D.1.3 Concurrent Programming},
    department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
    abstract = {Moderne Many-Core-Architekturen bieten ein sehr hohes Potenzial an
      Rechenleistung. Dies macht sie besonders f{\"u}r Anwendungen aus dem Bereich des
      wissenschaftlichen Hochleistungsrechnens und der Simulationstechnik attraktiv.
      Die Architekturen folgen dabei einem Ausf{\"u}hrungsparadigma, das sich am besten
      durch den Begriff “Many-Threading” beschreiben l{\"a}sst. Wie alle
      nanoelektronischen Halbleiterschaltungen leiden auch Many-Core-Prozessoren
      potentiell unter st{\"o}renden Einfl{\"u}ssen von transienten Fehlern (soft errors) und
      diversen Arten von Variationen. Diese Faktoren k{\"o}nnen die Zuverl{\"a}ssigkeit von
      Systemen negativ beeinflussen und erfordern Fehlertoleranz auf allen Ebenen,
      von der Hardware bis zur Software. Auf der Softwareseite stellt die
      Algorithmen-basierte Fehlertoleranz (ABFT) eine ausgereifte Technik zur
      Verbesserung der Zuverl{\"a}ssigkeit dar. Der Aufwand f{\"u}r die Anpassung dieser
      Technik an moderne Many-Threading-Architekturen darf jedoch keinesfalls
      untersch{\"a}tzt werden. In diesem Beitrag wird eine effiziente und fehlertolerante
      Abbildung der Matrixmultiplikation auf eine moderne Many-Core-Architektur
      pr{\"a}sentiert. Die Fehlertoleranz ist dabei integraler Bestandteil der Abbildung
      und wird durch ein ABFT-Schema realisiert, das die Leistung nur unwesentlich
      beeintr{\"a}chtigt.},
    url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2010-11&engl=0}
 }