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@inproceedings {INPROC-2010-91,
author = {Michael A. Kochte and Marcel Schaal and Hans-Joachim Wunderlich and Christian G. Zoellin},
title = {{Efficient Fault Simulation on Many-Core Processors}},
booktitle = {Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 13 - 18, 2010},
address = {New York, NY, USA},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {ACM Order Number},
volume = {4770101},
pages = {380--385},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2010},
isbn = {978-1-4503-0002-5},
issn = {0738-100X},
doi = {10.1145/1837274.1837369},
keywords = {Parallel Fault Simulation; Many-Core Processors; PPSFP},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://doi.acm.org/10.1145/1837274.1837369},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Fault simulation is essential in test generation, design for test and
reliability assessment of integrated circuits. Reliability analysis and the
simulation of self-test structures are particularly computationally expensive
as a large number of patterns has to be evaluated. In this work, we propose to
map a fault simulation algorithm based on the parallel-pattern single-fault
propagation (PPSFP) paradigm to many-core architectures and describe the
involved algorithmic optimizations. Many-core architectures are characterized
by a high number of simple execution units with small local memory. The
proposed fault simulation algorithm exploits the parallelism of these
architectures by use of parallel data structures. The algorithm is implemented
for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a
speed-up of up to 17x compared to an existing GPU fault-simulation algorithm
and up to 16x compared to state-of-the-art algorithms on conventional processor
architectures.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-91&engl=0}
}
@inproceedings {INPROC-2010-90,
author = {Michael A. Kochte and Christian G. Zoellin and Rafal Baranowski and Michael E. Imhof and Hans-Joachim Wunderlich and Nadereh Hatami and Stefano Di Carlo and Paolo Prinetto},
title = {{Effiziente Simulation von strukturellen Fehlern f{\"u}r die Zuverl{\"a}ssigkeitsanalyse auf Systemebene}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 66), 4. GMM/GI/ITG-Fachtagung; Wildbad Kreuth, Germany, September 13-15, 2010},
editor = {GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {66},
pages = {25--32},
type = {Konferenz-Beitrag},
month = {September},
year = {2010},
isbn = {978-3-8007-3299-9},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/453299003.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {In aktueller Prozesstechnologie muss die Zuverl{\"a}ssigkeit in allen
Entwurfsschritten von eingebetteten Systemen betrachtet werden. Methoden, die
nur Modelle auf unteren Abstraktionsebenen, wie Gatter- oder
Registertransferebene, verwenden, bieten zwar eine hohe Genauigkeit, sind aber
zu ineffizient, um komplexe Hardware/Software-Systeme zu analysieren. Hier
werden ebenen{\"u}bergreifende Verfahren ben{\"o}tigt, die auch hohe Abstraktion
unterst{\"u}tzen, um effizient die Auswirkungen von Defekten im System bewerten zu
k{\"o}nnen. Diese Arbeit stellt eine Methode vor, die aktuelle Techniken f{\"u}r die
effiziente Simulation von strukturellen Fehlern mit Systemmodellierung auf
Transaktionsebene kombiniert. Auf dieseWeise ist es m{\"o}glich, eine pr{\"a}zise
Bewertung der Fehlerauswirkung auf das gesamte Hardware/Software-System
durchzuf{\"u}hren. Die Ergebnisse einer Fallstudie eines Hardware/Software-Systems
zur Datenverschl{\"u}sselung und Bildkompression werden diskutiert und die Methode
wird mit einem Standard-Fehlerinjektionsverfahren verglichen.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-90&engl=0}
}
@inproceedings {INPROC-2010-88,
author = {B. Becker and S. Hellebrand and I. Polian and B. Straube and W. Vermeiren and H.-J. Wunderlich},
title = {{Massive statistical process variations: A grand challenge for testing nanoelectronic circuits}},
booktitle = {4th Workshop on Dependable and Secure Nanocomputing (WDSN10), Chicago, IL, USA, June 28 - July 01, 2010},
editor = {IFIP IEEE Computer Society},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {FP1041K-ART},
pages = {95--100},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2010},
isbn = {978-1-4244-7729-6},
doi = {10.1109/DSNW.2010.5542612},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Increasing parameter variations, high defect densities and a growing
susceptibility to external noise in nanoscale technologies have led to a
paradigm shift in design. Classical design strategies based on worst-case or
average assumptions have been replaced by statistical design, and new robust
and variation tolerant architectures have been developed. At the same time
testing has become extremely challenging, as parameter variations may lead to
an unacceptable behavior or change the impact of defects. Furthermore, for
robust designs a precise quality assessment is required particularly showing
the remaining robustness in the presence of manufacturing defects. The paper
pinpoints the key challenges for testing nanoelectronic circuits in more
detail, covering the range of variation-aware fault modeling via methods for
statistical testing and their algorithmic foundations to robustness analysis
and quality binning.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-88&engl=0}
}
@inproceedings {INPROC-2010-70,
author = {Claus Braun and Hans-Joachim Wunderlich},
title = {{Algorithm-based fault tolerance for many-core architectures}},
booktitle = {15th IEEE European Test Symposium (ETS'10); Praha, Czech Republic; May 24 - 28, 2010},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {CFP10216-USB},
pages = {253--253},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2010},
isbn = {978-1-4244-5833-2},
issn = {1530-1877},
doi = {10.1109/ETSYM.2010.5512738},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
C.1.4 Processor Architectures, Parallel Architectures,
C.4 Performance of Systems,
D.1.3 Concurrent Programming},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Modern many-core architectures with hundreds of cores provide a high
computational potential. This makes them particularly interesting for
scientific high-performance computing and simulation technology. Like all nano
scaled semiconductor devices, many-core processors are prone to reliability
harming factors like variations and soft errors. One way to improve the
reliability of such systems is software-based hardware fault tolerance. Here,
the software is able to detect and correct errors introduced by the hardware.
In this work, we propose a software-based approach to improve the reliability
of matrix operations on many-core processors. These operations are key
components in many scientific applications.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-70&engl=0}
}
@inproceedings {INPROC-2010-62,
author = {Christian G. Zoellin and Hans-Joachim Wunderlich},
title = {{Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes}},
booktitle = {IEEE VLSI Test Conference (VTS); Santa Cruz, CA, USA; April 18 - 21, 2010},
editor = {IEEE Computer Society},
publisher = {IEEE Computer Society},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {CFP10029-CDR},
pages = {380--385},
type = {Konferenz-Beitrag},
month = {April},
year = {2010},
isbn = {978-1-4244-6648-1},
issn = {1093-0167},
doi = {10.1109/VTS.2010.5469607},
keywords = {Delay test; power-aware testing; built-in self-test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {High delay-fault coverage requires rather sophisticated clocking schemes in
test mode, which usually combine launch-on-shift and launch-on-capture
strategies. These complex clocking schemes make low power test planning more
difficult as initialization, justification and propagation require multiple
clock cycles. This paper describes a unified method to map the sequential test
planning problem to a combinational circuit representation. The combinational
representation is subject to known algorithms for efficient low power built-in
self-test planning. Experimental results for a set of industrial circuits show
that even rather complex test clocking schemes lead to an efficient low power
test plan.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-62&engl=0}
}
@inproceedings {INPROC-2010-34,
author = {Melanie Elm and Hans-Joachim Wunderlich},
title = {{BISD: Scan-Based Built-In Self-Diagnosis}},
booktitle = {ACM/IEEE Design Automation and Test in Europe (DATE'10); Dresden, Germany; March 8-12, 2010},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {1243--1248},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2010},
isbn = {978-3-9810801-6-2},
keywords = {Logic BIST, Diagnosis},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5456997},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Built-In Self-Test (BIST) is less often applied to random logic than to
embedded memories due to the following reasons: Firstly, for a satisfiable
fault coverage it may be necessary to apply additional deterministic patterns,
which cause additional hardware costs. Secondly, the BIST-signature reveals
only poor diagnostic information. Recently, the first issue has been addressed
successfully. The paper at hand proposes a viable, effective and cost efficient
solution for the second problem. The paper presents a new method for Built-In
Self-Diagnosis (BISD). The core of the method is an extreme response compaction
architecture, which for the first time enables an autonomous on-chip evaluation
of test responses with negligible hardware overhead. The key advantage of this
architecture is that all data, which is relevant for a subsequent diagnosis, is
gathered during just one test session. The BISD method comprises a hardware
scheme, a test pattern generation approach and a diagnosis algorithm.
Experiments conducted with industrial designs substantiate that the additional
hardware overhead introduced by the BISD method is on average about 15\% of the
BIST area, and the same diagnostic resolution can be obtained as for external
testing.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2010-34&engl=0}
}
@inproceedings {INPROC-2009-59,
author = {Abdul-Wahid Hakmi and Stefan Holst and Hans-Joachim Wunderlich and Juergen Schloeffel and Friedrich Hapke and Andreas Glowatz},
title = {{Restrict Encoding for Mixed-Mode BIST}},
booktitle = {27th IEEE VLSI Test Symposium (VTS'09); Santa Cruz, California, USA; May 3-7, 2009},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3598},
pages = {179--184},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2009},
isbn = {978-0-7695-3598-2},
issn = {1093-0167},
doi = {10.1109/VTS.2009.43},
keywords = {Deterministic BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and
deterministic test. This paper presents a synthesis technique for a mixed-mode
BIST scheme which is able to exploit the regularities of a deterministic test
pattern set for minimizing the hardware overhead and memory requirements. The
scheme saves more than 50\% hardware costs compared with the best schemes known
so far while complete programmability is still preserved.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-59&engl=0}
}
@inproceedings {INPROC-2009-58,
author = {Stefan Holst and Hans-Joachim Wunderlich},
title = {{A diagnosis algorithm for extreme space compaction}},
booktitle = {Design, Automation and Test in Europe (DATE'09); Nice; France; April 20-24, 2009},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {CFP09162-DVD},
pages = {1355--1360},
type = {Konferenz-Beitrag},
month = {April},
year = {2009},
isbn = {978-1-4244-3781-8},
issn = {1530-1591},
isbn = {ieee: 5090875},
keywords = {Compaction; Design-for-test; Diagnosis; Embedded diagnosis; Multi-site test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090875},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {During volume testing, test application time, test data volume and high
performance automatic test equipment (ATE) are the major cost factors. Embedded
testing including built-in self-test (BIST) and multi-site testing are quite
effective cost reduction techniques which may make diagnosis more complex. This
paper presents a test response compaction scheme and a corresponding diagnosis
algorithm which are especially suited for BIST and multi-site testing. The
experimental results on industrial designs show, that test time and response
data volume reduces significantly and the diagnostic resolution even improves
with this scheme. A comparison with X-Compact shows, that simple parity
information provides higher diagnostic resolution per response data bit than
more complex signatures.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-58&engl=0}
}
@inproceedings {INPROC-2009-57,
author = {Michael A. Kochte and Christian G. Zoellin and Michael E. Imhof and Rauf Salimi Khaligh and Martin Radetzki and Hans-Joachim Wunderlich and Stefano Di Carlo and Prinetto Paolo},
title = {{Test Exploration and Validation Using Transaction Level Models}},
booktitle = {Design, Automation and Test in Europe (DATE'09); Nice; France; April 20-24, 2009},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {CFP09162-DVD},
pages = {1250--1253},
type = {Konferenz-Beitrag},
month = {April},
year = {2009},
isbn = {978-1-4244-3781-8},
issn = {1530-1591},
isbn = {ieee: 5090856},
keywords = {Test of systems-on-chip; design-for-test, transaction level modeling},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090856},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The complexity of the test infrastructure and test strategies in
systems-on-chip approaches the complexity of the functional design space. This
paper presents test design space exploration and validation of test strategies
and schedules using transaction level models (TLMs). All aspects of the test
infrastructure such as test access mechanisms, test wrappers, test data
compression and test controllers are modeled at transaction level. Since many
aspects of testing involve the transfer of a significant amount of test stimuli
and responses, the communication-centric view of TLMs suits this purpose
exceptionally well. A case study shows how TLMs can be used to efficiently
evaluate DfT decisions in early design steps and how to evaluate test
scheduling and resource partitioning during test planning. The presented
approach has significantly higher simulation efficiency than RTL and gate level
approaches.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-57&engl=0}
}
@inproceedings {INPROC-2009-56,
author = {Michael A. Kochte and Christian G. Zoellin and Michael E. Imhof and Rauf Salimi Khaligh and Martin Radetzki and Hans-Joachim Wunderlich and Stefano Di Carlo and Prinetto Paolo},
title = {{Test Exploration and Validation Using Transaction Level Models}},
booktitle = {Design, Automation and Test in Europe (DATE'09); Nice; France; April 20-24, 2009},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {1250--1253},
type = {Konferenz-Beitrag},
month = {April},
year = {2009},
isbn = {978-1-4244-3781-8},
issn = {1530-1591},
keywords = {Test of systems-on-chip; design-for-test; transaction level modeling},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The complexity of the test infrastructure and test strategies in
systems-on-chip approaches the complexity of the functional design space. This
paper presents test design space exploration and validation of test strategies
and schedules using transaction level models (TLMs). All aspects of the test
infrastructure such as test access mechanisms, test wrappers, test data
compression and test controllers are modeled at transaction level. Since many
aspects of testing involve the transfer of a significant amount of test stimuli
and responses, the communication-centric view of TLMs suits this purpose
exceptionally well. A case study shows how TLMs can be used to efficiently
evaluate DfT decisions in early design steps and how to evaluate test
scheduling and resource partitioning during test planning. The presented
approach has significantly higher simulation efficiency than RTL and gate level
approaches.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-56&engl=0}
}
@inproceedings {INPROC-2009-106,
author = {Melanie Elm and Hans-Joachim Wunderlich},
title = {{XP-SISR: Eingebaute Selbstdiagnose f{\"u}r Schaltungen mit Pr{\"u}fpfad}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 61), 3. GMM/GI/ITG-Fachtagung; Stuttgart, Germany, 21.09 - 23.09.2009},
editor = {GMM/VDE/VDI/ITG},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {61},
pages = {21--28},
type = {Konferenz-Beitrag},
month = {September},
year = {2009},
isbn = {978-3-8007-3178-7},
issn = {1432-341},
isbn = {docid: 453178004},
keywords = {Logic BIST; Diagnosis},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/453178004.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Die Vorteile des Eingebauten Selbsttests (BIST - Built-In Self-Test) sind
bekannt, f{\"u}r eingebettete Speicher ist BIST sogar die bevorzugte Teststrategie.
F{\"u}r freie Logik wird BIST deutlich seltener eingesetzt. Grund hierf{\"u}r ist zum
einen, dass deterministische Testmuster f{\"u}r eine hohe Fehlerabdeckung ben{\"o}tigt
werden und diese im Selbsttest hohe Kosten verursachen. Zum anderen lassen sich
aus den Testantworten, die zu einer einzigen Signatur kompaktiert werden, nur
wenige diagnostische Informationen ziehen. In den vergangenen Jahren wurden
kontinuierlich Fortschritte zur L{\"o}sung des ersten Problems erzielt. Dieser
Beitrag befasst sich mit der L{\"o}sung des zweiten Problems. Eine neue Methode f{\"u}r
die Eingebaute Selbstdiagnose (BISD - Built-In Self-Diagnosis) wird
vorgeschlagen. Kern der Methode ist eine kombinierte, extreme Raum- und
Zeitkompaktierung, die es erstmals erm{\"o}glicht, erwartete Antworten und
fehlerhafte Antworten mit vernachl{\"a}ssigbarem Aufwand auf dem zu testenden Chip
zu speichern. Somit k{\"o}nnen in einer einzigen Selbsttestsitzung pro Chip alle
zur Diagnose notwendigen Daten gesammelt werden. Das BISD Schema umfasst neben
der Kompaktierungshardware einen Diagnosealgorithmus und ein Verfahren zur
Testmustererzeugung, die Aliasingeffekte und die durch die starke Kompaktierung
verringerte diagnostische Aufl{\"o}sung kompensieren k{\"o}nnen. Experimente mit
aktuellen, industriellen Schaltungen zeigen, dass die diagnostische Aufl{\"o}sung
im Vergleich zum externen Test erhalten bleibt und der zus{\"a}tzliche
Hardware-Aufwand zu vernachl{\"a}ssigen ist.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-106&engl=0}
}
@inproceedings {INPROC-2009-105,
author = {Michael A. Kochte and Stefan Holst and Melanie Elm and Hans-Joachim Wunderlich},
title = {{Test Encoding for Extreme Response Compaction}},
booktitle = {14th IEEE European Test Symposium (ETS'09); Sevilla, Spain; May 25-29, 2009},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3703},
pages = {155--160},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2009},
isbn = {978-0-7695-3703-0},
issn = {1530-1877},
doi = {10.1109/ETS.2009.22},
keywords = {Design for Test; Embedded Diagnosis; Response Compaction; Test Compression},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Optimizing bandwidth by compression and compaction always has to solve the
trade-off between input bandwidth reduction and output bandwidth reduction.
Recently it has been shown that splitting scan chains into shorter segments and
compacting the shift data outputs into a singleparity bit reduces the test
response data to one bit per cycle without affecting fault coverage and
diagnostic resolution if the compactor's structure is included into the ATPG
process.This test data reduction at the output side comes with challenges at
the input side. The bandwidth requirement grows due to the increased number of
chains and due to a drastically decreased amount of don't care values in the
test patterns. The paper at hand presents a new iterative approach to test set
encoding which optimizes bandwidth on both input and output side while keeping
the diagnostic resolution and fault coverage. Experiments with industrial
designs demonstrate that test application time, test data volume and diagnostic
resolution are improved at the same time and for most designs testing with a
bandwidth of three bits per cycle is possible.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-105&engl=0}
}
@inproceedings {INPROC-2009-104,
author = {Michael A. Kochte and Christian G. Zoellin and Hans-Joachim Wunderlich},
title = {{Concurrent Self-Test with Partially Speci\&\#64257;ed Patterns For Low Test Latency and Overhead}},
booktitle = {14th IEEE European Test Symposium (ETS'09); Sevilla, Spain; May 25-29, 2009},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3703},
pages = {53--58},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2009},
isbn = {978-0-7695-3703-0},
issn = {1530-1877},
doi = {10.1109/ETS.2009.26},
keywords = {BIST; Concurrent self test; test generation},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Structural on-line self-test may be performed to detect permanent faults and
avoid their accumulation. This paper improves concurrent BIST techniques based
on a deterministic test set. Here, the test patterns are specially generated
with a small number of specified bits. This results in very low test latency,
which reduces the likelihood of fault accumulation. Experiments with a large
number of circuits show that the hardware overhead is significantly lower than
the overhead for previously published methods. Furthermore, the method allows
to tradeoff fault coverage, test latency and hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2009-104&engl=0}
}
@inproceedings {INPROC-2008-95,
author = {Michael E. Imhof and Hans-Joachim Wunderlich and Christian G. Zoellin},
title = {{Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 57), 2. GMM/GI/ITG-Fachtagung; Ingolstadt, Germany, 29.09 - 01.10.2008},
editor = {VDE/VDI and GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {57},
pages = {107--114},
type = {Konferenz-Beitrag},
month = {September},
year = {2008},
isbn = {978-3-8007-3119-0},
issn = {1432-3419},
isbn = {docid: 453119017},
keywords = {Robustes Design; Fehlertoleranz; Verlustleistung; Latch; Register; Single Event Effect},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/453119017.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {F{\"u}r Speicherfelder sind fehlerkorrigiernde Codes die vorherrschende Methode um
akzeptable Fehlerraten zu erreichen. In vielen aktuellen Schaltungen erreicht
die Zahl der Speicherelemente in freier Logik die Gr{\"o}{\ss}enordnung der Zahl von
SRAM-Zellen vor wenigen Jahren. Zur Reduktion der Verlustleistung wird h{\"a}ufig
der Takt der pegelgesteuerten Speicherelemente unterdr{\"u}ckt und die
Speicherlemente m{\"u}ssen ihren Zustand {\"u}ber lange Zeitintervalle halten. Die
Notwendigkeit der Absicherung der Speicherzellen wird zus{\"a}tzlich durch die
Miniaturisierung verst{\"a}rkt, die zu einer erh{\"o}hten Empfindlichkeit der
Speicherelemente gef{\"u}hrt hat.
Dieser Artikel stellt eine Methode zur fehlertoleranten Anordnung von
pegelgesteuerten Speicherelementen vor, die bei unterdr{\"u}cktem Takt
Einfachfehler lokalisieren und Mehrfachfehler detektieren kann. Bei aktiviertem
Takt k{\"o}nnen Einfach- und Mehrfachfehler erkannt werden. Die Register k{\"o}nnen
{\"a}hnlich wie Pr{\"u}fpfade effizient in den Entwurfsgang integriert werden. Die
Diagnoseinformation kann auf Modulebene leicht berechnet und genutzt werden.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-95&engl=0}
}
@inproceedings {INPROC-2008-94,
author = {Michael A. Kochte and Rafal Baranowski and Hans-Joachim Wunderlich},
title = {{Zur Zuverl{\"a}ssigkeitsmodellierung von Hardware-Software-Systemen}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 57), 2. GMM/GI/ITG-Fachtagung; Ingolstadt, Germany, 29.09 - 01.10.2008},
editor = {VDE/VDI and GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {57},
pages = {83--90},
type = {Konferenz-Beitrag},
month = {September},
year = {2008},
isbn = {978-3-8007-3119-0},
issn = {1432-3419},
isbn = {docid: 453119013},
keywords = {Modellierung; Zuverl{\"a}ssigkeit; eingebettete Systeme; System-Level; Systems-on-Chip},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/453119013.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Zur Zuverl{\"a}ssigkeitsanalyse von Hardware-Software-Systemen ist ein Systemmodell
notwendig, welches sowohl Struktur und Architektur der Hardware als auch die
ausgef{\"u}hrte Funktion betrachtet. Wird einer dieser Aspekte des Gesamtsystems
vernachl{\"a}ssigt, kann sich eine zu optimische oder zu konservative Sch{\"a}tzung der
Zuverl{\"a}ssigkeit ergeben.
Ein reines Strukturmodell der Hardware erlaubt, den Einfluss von logischer und
struktureller Fehlermaskierung auf die Fehlerh{\"a}ufigkeit der Hardware zu
bestimmen. Allerdings kann ein solches Modell nicht die Fehlerh{\"a}ufigkeit des
Gesamtsystems hinreichend genau sch{\"a}tzen. Die Ausf{\"u}hrung der Funktion auf dem
System f{\"u}hrt zu speziellen Nutzungs- und Kommunikationsmustern der
Systemkomponenten, die zu erh{\"o}hter oder verminderter Anf{\"a}lligkeit gegen{\"u}ber
Fehlern f{\"u}hren.
Diese Arbeit motiviert die Modellierung funktionaler Aspekte zusammen mit der
Struktur des Systems. Mittels Fehlerinjektion und Simulation wird der starke
Einfluss der Funktion auf die Fehleranf{\"a}lligkeit des Systems aufgezeigt. Die
vorgestellte Methodik, funktionale Aspekte mit in die
Zuverl{\"a}ssigkeitsmodellierung einzubinden, verspricht eine realistischere
Bewertung von Hardware-Software-Systemen},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-94&engl=0}
}
@inproceedings {INPROC-2008-75,
author = {Michael E. Imhof and Hans-Joachim Wunderlich and Christian G. Zoellin},
title = {{Integrating Scan Design and Soft Error Correction in Low-Power Applications}},
booktitle = {Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS'08); Rhodes, Greece, July 7-9, 2008},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3264},
pages = {59--64},
type = {Konferenz-Beitrag},
month = {Juli},
year = {2008},
isbn = {978-0-7695-3264-6},
doi = {10.1109/IOLTS.2008.31},
keywords = {Robust design; fault tolerance; latch; low power; register; single event effects},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Error correcting coding is the dominant technique to achieve acceptable
soft-error rates in memory arrays. In many modern circuits, the number of
memory elements in the random logic is in the order of the number of SRAM cells
on chips only a few years ago. Often latches are clock gated and have to retain
their states during longer periods. Moreover, miniaturization has led to
elevated susceptibility of the memory elements and further increases the need
for protection. This paper presents a fault-tolerant register latch
organization that is able to detect single-bit errors while it is clock gated.
With active clock, single and multiple errors are detected. The registers can
be efficiently integrated similar to the scan design flow, and error detecting
or locating information can be collected at module level. The resulting
structure can be efficiently reused for offline and general online testing.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-75&engl=0}
}
@inproceedings {INPROC-2008-66,
author = {Melanie Elm and Hans-Joachim Wunderlich and Michael E. Imhof and Christian G. Zoellin and Jens Leenstra and Nicolas Maeding},
title = {{Scan Chain Clustering for Test Power Reduction}},
booktitle = {Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008},
address = {New York, NY, USA},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {ACM Order Number},
volume = {477081},
pages = {828--833},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2008},
isbn = {978-1-60558-115-6},
isbn = {ISSN 0738-100X},
doi = {10.1145/1391469.1391680},
keywords = {Test; Design for Test; Low Power; Scan Design},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {An effective technique to save power during scan based test is to switch off
unused scan chains. The results obtained with this method strongly depend on
the mapping of scan flip-flops into scan chains, which determines how many
chains can be deactivated per pattern. In this paper, a new method to cluster
flip-flops into scan chains is presented, which minimizes the power consumption
during test. The approach does not specify any ordering inside the chains and
fits seamlessly to any standard tool for scan chain integration. The
application of known test power reduction techniques to the optimized scan
chain configurations shows significant improvements for large industrial
circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-66&engl=0}
}
@inproceedings {INPROC-2008-65,
author = {Christian G. Zoellin and Hans-Joachim Wunderlich and Ilia Polian and Bernd Becker},
title = {{Selective Hardening in Early Design Steps}},
booktitle = {Proceedings of the 13th IEEE European Test Symposium (ETS'08), Lago Maggiore, Italy, May 25-29, 2008},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {185--190},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2008},
isbn = {978-0-7695-3150-2},
issn = {1530-1877},
doi = {10.1109/ETS.2008.30},
keywords = {Soft error mitigation; reliability},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Hardening a circuit against soft errors should be performed in early design
steps before the circuit is laid out. A viable approach to achieve soft error
rate (SER) reduction at a reasonable cost is to harden only parts of a circuit.
When selecting which locations in the circuit to harden, priority should be
given to critical spots for which an error is likely to cause a system
malfunction. The criticality of the spots depends on parameters not all
available in early design steps. We employ a selection strategy which takes
only gate-level information into account and does not use any low-level
electrical or timing information. We validate the quality of the solution using
an accurate SER estimator based on the new UGC particle strike model. Although
only partial information is utilized for hardening, the exact validation shows
that the susceptibility of a circuit to soft errors is reduced significantly.
The results of the hardening strategy presented are also superior to known
purely topological strategies in terms of both hardware overhead and
protection.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-65&engl=0}
}
@inproceedings {INPROC-2008-36,
author = {Michael A. Kochte and Ramesh Natarajan},
title = {{A framework for scheduling parallel dbms user-defined programs on an attached high-performance computer}},
booktitle = {Proceedings of the 2008 conference on Computing frontiers:CF'08; Ischia, Italy May 5-7, 2008},
publisher = {Association for Computing Machinery, Inc. (ACM)},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {97--104},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2008},
isbn = {978-1-60558-077-7},
doi = {10.1145/1366230.1366245},
keywords = {database accelerators; high-performance computing; parallel user-defined programs},
language = {Englisch},
cr-category = {C.1.4 Processor Architectures, Parallel Architectures},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {We describe a software framework for deploying, scheduling and executing
parallel DBMS user-defined programs on an attached high-performance computer
(HPC) platform. This framework is advantageous for many DBMS workloads in the
following two aspects. First, the long-running user-defined programs can be
speeded up by taking advantage of the greater hardware parallelism available on
the attached HPC platform. Second, the interactive response time of the
remaining applications on the database server platform is improved by the
off-loading of long-running user-defined programs to the attached HPC platform.
Our framework provides a new approach for integrating high-performance
computing into the workflow of query-oriented, computationally-intensive
applications.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-36&engl=0}
}
@inproceedings {INPROC-2008-35,
author = {Uranmandakh Amgalan and Christian Hachmann and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Signature Rollback – A Technique for Testing Robust Circuits}},
booktitle = {Proceedings of the 26th IEEE VLSI Test Symposium (VTS'08); San Diego, California, USA; Apr 27th - May 1st, 2008},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3123},
pages = {125--130},
type = {Konferenz-Beitrag},
month = {April},
year = {2008},
isbn = {978-0-7695-3123-6},
issn = {1093-0167},
doi = {10.1109/VTS.2008.34},
keywords = {Embedded Test; Robust Design; Rollback and Recovery; Test Quality and Reliability; Time Redundancy},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Dealing with static and dynamic parameter variations has become a major
challenge for design and test. To avoid unnecessary yield loss and to ensure
reliable system operation a robust design has become mandatory. However,
standard structural test procedures still address classical fault models and
cannot deal with the non-deterministic behavior caused by parameter variations
and other reasons. Chips may be rejected, even if the test reveals only
non-critical failures that could be compensated during system operation. This
paper introduces a scheme for embedded test, which can distinguish critical
permanent and noncritical transient failures for circuits with time redundancy.
To minimize both yield loss and the overall test time, the scheme relies on
partitioning the test into shorter sessions. If a faulty signature is observed
at the end of a session, a rollback is triggered, and this particular session
is repeated. An analytical model for the expected overall test time provides
guidelines to determine the optimal parameters of the scheme.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-35&engl=0}
}
@inproceedings {INPROC-2008-24,
author = {Melanie Elm and Hans-Joachim Wunderlich},
title = {{Scan Chain Organization for Embedded Diagnosis}},
booktitle = {Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {CFP08162-DVD},
pages = {468--473},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2008},
isbn = {978-3-9810801-3-1},
doi = {10.1109/DATE.2008.4484725},
keywords = {design for diagnosis; embedded test; scan design},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Keeping diagnostic resolution as high as possible while maximizing the
compaction ratio is subject to research since the advent of embedded test. In
this paper, we present a novel scan design methodology to maximize diagnostic
resolution when compaction is employed. The essential idea is to consider the
diagnostic resolution during the clustering of scan elements to scan chains.
Our methodology does not depend on a fault model and is helpful with any type
of compactor.
A linear time heuristic is presented to solve the scan chain clustering
problem. We evaluate our approach for industrial and academic benchmark
circuits. It turns out to be superior to both random and to layout driven scan
chain clustering. The methodology is applicable to any gate-level design and
fits smoothly into an industrial design flow.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-24&engl=0}
}
@inproceedings {INPROC-2008-22,
author = {Michael A. Kochte and Christian G. Zoellin and Michael E. Imhof and Hans-Joachim Wunderlich},
title = {{Test Set Stripping Limiting the Maximum Number of Specified Bits}},
booktitle = {Proc. of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08); Hong Kong, SAR, China, 23-25 January 2008,},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P3110},
pages = {581--586},
type = {Konferenz-Beitrag},
month = {Januar},
year = {2008},
isbn = {978-0-7695-3110-6},
doi = {10.1109/DELTA.2008.64},
keywords = {test relaxation; test generation; tailored ATPG},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.ece.ust.hk/delta2008/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {This paper presents a technique that limits the maximum number of specified
bits of any pattern in a given test set. The outlined method uses algorithms
similar to ATPG, but exploits the information in the test set to quickly find
test patterns with the desired properties. The resulting test sets show a
significant reduction in the maximum number of specified bits in the test
patterns. Furthermore, results for commercial ATPG test sets show that even the
overall number of specified bits is reduced substantially},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2008-22&engl=0}
}
@inproceedings {INPROC-2007-88,
author = {Bernd Becker and Sybille Hellebrand and Bernd Straube and Hans-Joachim Wunderlich},
title = {{Test und Zuverl{\"a}ssigkeit nanoelektronischer Systeme}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 52), 1. GMM/GI/ITG-Fachtagung; M{\"u}nchen, Germany, 26.03. - 28.03.2007},
editor = {GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {52},
pages = {139--140},
type = {Konferenz-Beitrag},
month = {April},
year = {2007},
isbn = {978-3-8007-3023-0},
isbn = {docid: 463023018},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/463023018.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Neben der zunehmenden Anf{\"a}lligkeit gegen{\"u}ber Fertigungsfehlern bereiten
insbesondere vermehrte Parameterschwankungen, zeitabh{\"a}ngige Materialver{\"a}nderung
St{\"o}ranf{\"a}lligkeit w{\"a}hrend des Betriebs massive Probleme bei der
Qualit{\"a}tssicherung f{\"u}r nanoelektronische Systeme. F{\"u}r eine wirtschaftliche
Produktion und einen zuverl{\"a}ssigen Systembetrieb wird einerseits ein robuster
Entwurf unabdingbar, andererseits ist damit auch ein Paradigmenwechsel beim
Test erforderlich. Anstatt lediglich defektbehaftete Systeme zu erkennen und
auszusortieren, muss der Test bestimmen, ob ein System trotz einer gewissen
Menge von Fehlern funktionsf{\"a}hig ist, und die verbleibende Robustheit gegen{\"u}ber
St{\"o}rungen im Betrieb charakterisieren. Im Rahmen des Projekts RealTest werden
einheitliche Entwurfs- und Teststrategien entwickelt, die sowohl einen robusten
Entwurf als auch eine darauf abgestimmte Qualit{\"a}tssicherung unterst{\"u}tzen.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-88&engl=0}
}
@inproceedings {INPROC-2007-87,
author = {Michael E. Imhof and Christian G. Zoellin and Hans-Joachim Wunderlich and Nicolas Maeding and Jens Leenstra},
title = {{Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverl{\"a}ssigkeit und Ausbeute}},
booktitle = {Zuverl{\"a}ssigkeit und Entwurf (GMM-FB 52), 1. GMM/GI/ITG-Fachtagung; M{\"u}nchen, Germany, 26.03. - 28.03.2007},
editor = {GMM},
address = {Berlin},
publisher = {VDE Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {GMM-Fachbericht},
volume = {52},
pages = {69--76},
type = {Konferenz-Beitrag},
month = {April},
year = {2007},
isbn = {978-3-8007-3023-0},
isbn = {docid: 463023008},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.vde-verlag.de/proceedings-de/463023008.html},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Die stark erh{\"o}hte durchschnittliche und maximale Verlustleistung w{\"a}hrend des
Tests integrierter Schaltungen kann zu einer Beeintr{\"a}chtigung der Ausbeute bei
der Produktion sowie der Zuverl{\"a}ssigkeit im sp{\"a}teren Betrieb f{\"u}hren. Wir
stellen eine Testplanung f{\"u}r Schaltungen mit parallelen Pr{\"u}fpfaden vor, welche
die Verlustleistung w{\"a}hrend des Tests reduziert. Die Testplanung wird auf ein
{\"U}berdeckungsproblem abgebildet, das mit einem heuristischen L{\"o}sungsverfahren
effizient auch f{\"u}r gro{\ss}e Schaltungen gel{\"o}st werden kann. Die Effizienz des
vorgestellten Verfahrens wird sowohl f{\"u}r die bekannten Benchmarkschaltungen als
auch f{\"u}r gro{\ss}e industrielle Schaltungen demonstriert.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-87&engl=0}
}
@inproceedings {INPROC-2007-86,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Rio Mascarenhas and Juergen Schloeffel and Garbers Michael},
title = {{Synthesis of Irregular Combinational Functions with Large Don't Care Sets}},
booktitle = {Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, Stresa-Lago Maggiore, Italy, March 11-13, 2007},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {287--292},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2007},
isbn = {978-1-59593-605-9},
doi = {10.1145/1228784.1228856},
keywords = {logic synthesis; incompletely specified functions},
language = {Englisch},
cr-category = {B.6.3 Logic Design, Design Aids},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {A special logic synthesis problem is considered for Boolean functions which
have large don't care sets and are irregular. Here, a function ist considered
as irregular if the input assignments mapped to specified values ('1'or'0') are
randomly spread over the definition space. Such functions can be encounted in
the field of design for test. The proposed method uses ordered BDDs for logic
manipulations and generates freeBDD-like covers. For the considered benchmark
functions, implementations were found with the significant reduction of the
node/gate count as compared to SIS or the methodes offered by a
state-of-the-art BDD package.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-86&engl=0}
}
@inproceedings {INPROC-2007-79,
author = {Abdul-Wahid Hakmi and Hans-Joachim Wunderlich and Christian G. Zoellin and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Laurent Souef},
title = {{Programmable Deterministic Built-in Self-test}},
booktitle = {Proc. of the International Test Conference (ITC); Santa Clara, CA, USA; October 23-25, 2007},
editor = {International Test Conference},
address = {Washington, D.C.},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {07CH37892C},
pages = {1--9},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2007},
isbn = {978-1-4244-1127-6},
issn = {1089-3539},
doi = {10.1109/TEST.2007.4437611},
keywords = {Deterministic BIST; Test data compression},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {In this paper, we propose a new programmable deterministic Built-In Self-Test
(BIST) method that requires significantly lower storage for deterministic
patterns than existing programmable methods and provides high flexibility for
test engineering in both internal and external test. Theoretical analysis
suggests that significantly more care bits can be encoded in the seed of a
Linear Feedback Shift Register (LFSR), if a limited number of conflicting
equations is ignored in the employed linear equation system. The ignored care
bits are separately embedded into the LFSR pattern. In contrast to known
deterministic BIST schemes based on test set embedding, the embedding logic
function is not hardwired. Instead, this information is stored in memory using
a special compression and decompression method. Experiments for benchmark
circuits and industrial designs demonstrate that the approach has considerably
higher overall coding efficiency than the existing methods.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-79&engl=0}
}
@inproceedings {INPROC-2007-78,
author = {Sybille Hellebrand and Christian G. Zoellin and Hans-Joachim Wunderlich and Stefan Ludwig and Torsten Coym and Bernd Straube},
title = {{A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction}},
booktitle = {Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2885},
pages = {50--58},
type = {Konferenz-Beitrag},
month = {September},
year = {2007},
isbn = {0-7695-2885-6},
issn = {1550-5774},
doi = {10.1109/DFT.2007.43},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/servlet/opac?punumber=4358358},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Decreasing feature sizes have led to an increased vulnerability of random logic
to soft errors. In combinational logic a particle strike may lead to a glitch
at the output of a gate, also referred to as single even transient (SET), which
in turn can propagate to a register and cause a single event upset (SEU) there.
Circuit level modeling and analysis of SETs provides an attractive compromise
between computationally expensive simulations at device level and less accurate
techniques at higher levels. At the circuit level particle strikes crossing a
pn-junction are traditionally modeled with the help of a transient current
source. However, the common models assume a constant voltage across the
pn-junction, which may lead to inaccurate predictions concerning the shape of
expected glitches. To overcome this problem, a refined circuit level model for
strikes through pnjunctions is investigated and validated in this paper. The
refined model yields significantly different results than common models. This
has a considerable impact on SEU prediction, which is confirmed by extensive
simulations at gate level. In most cases, the refined, more realistic, model
reveals an almost doubled risk of a system failure after an SET.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-78&engl=0}
}
@inproceedings {INPROC-2007-77,
author = {Sybille Hellebrand and Christian G. Zoellin and Hans-Joachim Wunderlich and Stefan Ludwig and Torsten Coym and Bernd Straube},
title = {{Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)}},
booktitle = {Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia,September 12-14, 2007},
address = {Ljubljana},
publisher = {MIDEM},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {3--10},
type = {Konferenz-Beitrag},
month = {September},
year = {2007},
isbn = {978-961-91023-7-4},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The increased number of fabrication defects, spatial and temporal variability
of parameters, as well as the growing impact of soft errors in nanoelectronic
systems require a paradigm shift in design, verification and test. A robust
design becomes mandatory to ensure dependable systems and acceptable yields.
Design robustness, however, invalidates many traditional approaches for testing
and implies enormous challenges. The RealTest Project addresses these problems
for nanoscale CMOS and targets unified design and test strategies to support
both a robust design and a coordinated quality assurance after manufacturing
and during the lifetime of a system. The paper first gives a short overview of
the research activities within the project and then focuses on a first result
concerning soft errors in combinational logic. It will be shown that common
electrical models for particle strikes in random logic have underestimated the
effects on the system behavior. The refined model developed within the RealTest
Project predicts about twice as many single events upsets (SEUs) caused by
particle strikes as traditional models.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-77&engl=0}
}
@inproceedings {INPROC-2007-76,
author = {Hans-Joachim Wunderlich and Melani Elm and Stefan Holst},
title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper)}},
booktitle = {Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07); Bled, Slovenia; September 2007},
address = {Ljubljana},
publisher = {MIDEM},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {27--36},
type = {Konferenz-Beitrag},
month = {September},
year = {2007},
isbn = {978-961-91023-7-4},
keywords = {Diagnosis; Debug; Embedded Test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Rising design complexity and shrinking structures pose new challenges for debug
and diagnosis. Finding bugs and defects quickly during the whole life cycle of
a product is crucial for time to market, time to volume and improved product
quality. Debug of design errors and diagnosis of defects have many common
aspects. In this paper we give an overview of state of the art algorithms,
which tackle both tasks, and present an adaptive approach to design debug and
logic diagnosis.
Special design for diagnosis is needed to maintain visibility of internal
states and diagnosability of deeply embedded cores. This article discusses
current approaches to design for diagnosis to support all debug tasks from
first silicon to the system level.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-76&engl=0}
}
@inproceedings {INPROC-2007-33,
author = {Michael Wedel and Peter G{\"o}hner and Jochen G{\"a}ng and Bernd Bertsche and Talal Arnaout and Hans-Joachim Wunderlich},
title = {{Dom{\"a}nen{\"u}bergreifende Zuverl{\"a}ssigkeitsbewertung in fr{\"u}hen Entwicklungsphasen unter Ber{\"u}cksichtigung von Wechselwirkungen}},
booktitle = {5. Paderborner Workshop ``Entwurf mechatronischer Systeme''},
address = {Paderborn},
publisher = {HNI Verlag},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {HNI Verlagsschriftenreihe},
volume = {210},
pages = {257--272},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2007},
keywords = {Zuverl{\"a}ssigkeitsbewertung mechatronischer Systeme; fr{\"u}he Entwicklungsphasen; dom{\"a}nen{\"u}bergreifende Wechselwirkungen; quantitative und qualitative Methoden},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Aufgrund der unvollst{\"a}ndigen Informationen {\"u}ber ein mechatronisches System
stellt die fr{\"u}he Zuverl{\"a}ssigkeitsbewertung eine gro{\ss}e Herausforderung dar.
Um die jeweiligen Vorteile zu nutzen, wurden klassische Ans{\"a}tze in den
einzelnen Dom{\"a}nen kombiniert und in eine ganzheitliche Methode zur
Zuverl{\"a}ssigkeitsbewertung in den fr{\"u}hen Entwicklungsphasen integriert. In
Zusammenarbeit verschiedener Ingenieursdisziplinen wurde die ganzheitliche
Methode um die rechnergest{\"u}tzte Ermittlung von Fehlerzusammenh{\"a}ngen im Rahmen
einer Risikoabsch{\"a}tzung und verschiedene qualitative Modellierungs- und
Analyseans{\"a}tze erweitert. F{\"u}r die systematische Analyse des wechselseitigen
Einflusses der beteiligten Dom{\"a}nen und die Integration in die
Zuverl{\"a}ssigkeitsbewertung wurden Wechselwirkungen zwischen den Dom{\"a}nen
untersucht und klassifiziert.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-33&engl=0}
}
@inproceedings {INPROC-2007-32,
author = {Stefan Holst and Hans-Joachim Wunderlich},
title = {{Adaptive Debug and Diagnosis without Fault Dictionaries}},
booktitle = {12th IEEE European Test Symposium (ETS'07); Freiburg, Germany; May 21-24, 2007},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2827},
pages = {7--12},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2007},
isbn = {0-7695-2827-9},
issn = {1530-1877},
doi = {10.1109/ETS.2007.9},
keywords = {Diagnosis; Debug; Test; VLSI},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.cad.polito.it/~ets08/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Diagnosis is essential in modern chip production to increase yield, and debug
constitutes a major part in the presilicon development process. For recent
process technologies, defect mechanisms are increasingly complex, and
continuous efforts are made to model these defects by using sophisticated fault
models. Traditional static approaches for debug and diagnosis with a simplified
fault model are more and more limited. In this paper, a method is presented,
which identifies possible faulty regions in a combinational circiut, based on
its input/output behavior and independent of a fault model. The new adaptive,
statistical approach combines a flexible and powerful effect-cause pattern
analysis algorithm with high-resolution ATPG. We show the effectiveness of the
approach through experiments with benchmark and industrial circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-32&engl=0}
}
@inproceedings {INPROC-2007-31,
author = {Phillip Oehler and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}},
booktitle = {12th IEEE European Test Symposium (ETS'07); Freiburg, Germany; May 21-24, 2007},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2827},
pages = {91--96},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2007},
isbn = {0-7695-2827-9},
issn = {1530-1877},
doi = {10.1109/ETS.2007.10},
keywords = {Memory repair; BIRA; 2D redundancy},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {An efficient on-chip infrastructure for memory test and repair is crucial to
enhance yield and availability of SoCs. A commonly used repair strategy is to
equip memories with spare rows and columns (2D redundancy). Although exact
algorithms are available for offline repair analysis, they cannot be directly
applied on-chip because of the prohibitive storage requirements for failture
bitmaps and the complex data structures inherent in the algorithms. Existing
heuristics for built-in repair analysis (BIRA) try to circumvent this problem
either by very simple search strategies or by restricting the search to smaller
local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible
repair combination. While a parallel implementation suffers from a high
hardware overhead, a serial implementation leads to high test times. The
integrated built-in test and repair approach proposed in this paper interleaves
test and repair analysis and supports an exact solution without failure bitmap.
The search can be implemented with a stack, which is limited by the number of
redundant elements. The basic search procedure is combined with an efficient
technique to continuously reduce the problem complexity and keep the test and
analysis time low.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-31&engl=0}
}
@inproceedings {INPROC-2007-30,
author = {Phillip Oehler and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair}},
booktitle = {Proceedings 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, Poland, April 2007},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {1--6},
type = {Konferenz-Beitrag},
month = {April},
year = {2007},
isbn = {1-4244-1161-0},
doi = {10.1109/DDECS.2007.4295278},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ui.sav.sk/DDECS2008/},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {An efficient on-chip infrastructure for memory test and repair is crucial to
enhance yield and availability of SoCs. A commonly used repair strategy is to
equip memories with spare rows and columns (2D redundancy). To advoid the
prohibitive storage requirements for failure bitmaps and the complex data
structures inherent in most algorithms for offline repair analysis, existing
heuristics for built-in repair analysis (BIRA) either use very simple search
strategies or restict the search to smaller local bitmaps. Exact BIRA
algorithms work with sub analyzers for each possible repair combination. While
a parallel implementation suffers from a high hardware overhead, a serial
implementation leads to increased test times. Recently an integrated built-in
test and repair approach has been proposed which interleaves test and repair
analysis and supports an exact solution with moderate hardware overhead and
reasonable test times. The search is based on a depth first traversal of a
binary tree, which can be efficiently implemented using a stack of limited
size. This algorithm can be realized with different repair strategies guiding
the selection of spare rows or columns in each step. In this paper the impact
of four different repair strategies on the test and repair time is analyzed.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-30&engl=0}
}
@inproceedings {INPROC-2007-25,
author = {Michael E. Imhof and Christian G. Zoellin and Hans-Joachim Wunderlich and Nicolas Maeding and Jens Leenstra},
title = {{Scan Test Planning for Power Reduction}},
booktitle = {44th ACM/IEEE Design Automation Conference (DAC), San Diego, Ca, USA, June 4-8, 2007},
publisher = {Association for Computing Machinery},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {521--526},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2007},
isbn = {978-1-59593-627-1},
issn = {0738-100X},
doi = {10.1145/1278480.1278614},
keywords = {test planning; power during test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www2.dac.com/44th+dac+_2007_.aspx},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Many STUMPS architectures found in current chip designs allow disabling of
individual scan chains for debug and diagnosis. In a recent paper it has been
shown that this feature can be used for reducing the power consumption during
test. Here, we present an efficient algorithm for the automated generation of a
test plan that keeps fault coverage as well as test time, while significantly
reducing the amount of wasted energy. A fault isolation table, which is usually
used for diagnosis and debug, is employed to accurately determine scan chains
that can be disabled. The algorithm was successfully applied to large
industrial circuits and identifies a very large amount of excess pattern shift
activity.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2007-25&engl=0}
}
@inproceedings {INPROC-2006-80,
author = {Talal Arnaout and Guenter Bartsch and Hans-Joachim Wunderlich},
title = {{Some Common Aspects of Design Validation, Debug and Diagnosis}},
booktitle = {Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06); Kuala Lumpur, Malaysia; January 17-19, 2006},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2500},
pages = {3--8},
type = {Workshop-Beitrag},
month = {Januar},
year = {2006},
isbn = {0-7695-2500-8},
doi = {10.1109/DELTA.2006.79},
language = {Englisch},
cr-category = {B.8 Performance and Reliability},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Design, Verification and Test of integrated circuits with millions of gates put
strong requirements on design time, test volume, test application time, test
speed and diagnostic resolution. In this paper, an overview is given on the
common aspects of these tasks and how they interact. Diagnosis techniques may
be used after manufacturing, for chip characterization and field return
analysis, and even for rapid prototyping.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-80&engl=0}
}
@inproceedings {INPROC-2006-79,
author = {Jun Zhou and Hans-Joachim Wunderlich},
title = {{Software-Based Self-Test of Processors under Power Constraints}},
booktitle = {Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE'06); Munich, Germany; March 06 - 10, 2006},
editor = {European Design and Automation Association},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {430--436},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2006},
isbn = {3-9810801-0-6},
doi = {10.1109/DATE.2006.243798},
keywords = {test program generation; processor test; low power test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1656919},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Software-based self-test (SBST) of processors offers many benefits, such as
dispense with expensive test equipments, test execution during maintenance and
in the field or initialization tests for the whole system. In this paper, for
the first time a structural SBST methodology is proposed which optimizes
energy, average power consumption, test length and fault coverage at the same
time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-79&engl=0}
}
@inproceedings {INPROC-2006-78,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Juergen Schloeffel and Michael Garbers},
title = {{Deterministic Logic BIST for Transition Fault Testing}},
booktitle = {Proceedings of the European Test Symposium (ETS'06); Southampton, UK; May 22 - 25, 2006},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2566},
pages = {123--128},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2006},
isbn = {0-7695-2566-0},
issn = {1530-1877},
doi = {10.1109/ETS.2006.12},
keywords = {deterministic logic BIST; delay test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {BIST is an attractive approach to detect delay faults due to its inherent
support for at-speed test. Deterministic logic BIST (DLBIST) is a technique
which was successfully applied to stuck-at fault testing. As delay faults have
lower random pattern testability than stuck-at faults, the need for DLBIST
schemes is increased. Nevertheless, an extension to delay fault testing is not
trivial, since this necessitates the application of pattern pairs.
Consequently, delay fault testing is expected to require a larger mapping
effort and logic overhead than stuck-at fault testing. In this paper, we
consider the so-called transition fault model, which is widely used for
complexity reasons. We present an extension of a DLBIST scheme for transition
fault testing. Functional justification is used to generate the required
pattern pairs. The efficiency of the extended scheme is investigated by using
industrial benchmark circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-78&engl=0}
}
@inproceedings {INPROC-2006-77,
author = {Nabil Badereddine and Patrick Girard and Serge Pravossoudovitch and Christian Landrault and Arnaud Virazel and Hans-Joachim Wunderlich},
title = {{Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics}},
booktitle = {Proceedings of the Conference on Design \& Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, September 5 - 7, 2006},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {359--364},
type = {Konferenz-Beitrag},
month = {September},
year = {2006},
isbn = {0-7803-9727-4},
doi = {10.1109/DTIS.2006.1708693},
keywords = {Dft; scan testing; power-aware testing; peak power consumption},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Scan architectures, though widely used in modern designs, are expensive in
power consumption. In this paper, we discuss the issues of excessive peak power
consumption during scan testing. We show that taking care of high current
levels during the test cycle (i.e. between launch and capture) is highly
relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose
a solution based on power-aware assignment of don´t care bits in deterministic
test patterns. For ISCAS´89 and ITC´99 benchmark circuits, this approach
reduces peak power during the test cycle up to 89\% compared to a random filling
solution.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-77&engl=0}
}
@inproceedings {INPROC-2006-76,
author = {Nabil Badereddine and Patrick Girard and Serge Pravossoudovitch and Christian Landrault and Virazel Arnaud and Hans-Joachim Wunderlich},
title = {{Structural-based Power-aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing}},
booktitle = {Proceedings of the IFIP International Conference on Very Large Scale Integration (vlsi-soc), Nice, France, October 16 - 18},
publisher = {International Federation for Information Processing},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {403--408},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2006},
isbn = {3-901882-19-7},
doi = {10.1109/VLSISOC.2006.313222},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Scan architectures, though widely used in modern designs for testing purpose,
are expensive in power consumption. In this paper, we first discuss the issues
of excessive peak power consumption during scan testing. We next show that
taking care of high current levels during the test cycle (i.e. between launch
and capture) is highly relevant so as to avoid noise phenomena such as irdrop
or ground bounce. Then, we propose a solution based on power-aware assignment
of don´t care bits in deterministic test patterns that considers structural
information of the circuit under test. Experiments have been performed on
ISCAS´89 and ITC´99 benchmark circuits with the proposed structural-based
power-aware X-Filling technique. These results show that the proposed technique
provides the best tradeoff between peak power reduction and increase of test
sequence length.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-76&engl=0}
}
@inproceedings {INPROC-2006-75,
author = {Christian Zoellin and Hans-Joachim Wunderlich and Nicolas Maeding and Jens Leenstra},
title = {{BIST Power Reduction Using Scan-Chain Disable in the Cell Processor}},
booktitle = {Proceedings of the International Test Conference (ITC); Santa Clara, CA, USA; October 24 - 26, 2006},
editor = {International Test Conference},
address = {Washington, D.C.},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {06CH37787},
pages = {1--8},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2006},
isbn = {1-4244-0292-1},
issn = {1089-3539},
doi = {10.1109/TEST.2006.297695},
keywords = {microprocessor test; BIST; low power test.},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Built-in self test is a major part of the manufacturing test procedure for the
Cell Processor. However, pseudo random patterns cause a high switching activity
which is not effectively reduced by standard low power design techniques. If
special care is not taken, the scan-speed may have to be reduced significantly,
thus extending test time and costs. In this paper, we describe a test power
reduction method for logic BIST which uses test scheduling, planning and
scan-gating. In LBIST, effective patterns that detect additional faults are
very scarce after a few dozens of scan cycles and often less than one pattern
in a hundred detects new faults. In most cases, such an effective pattern
requires only a reduced set of the available scan chains to detect the fault
and all don´t-care scan chains can be disabled, therefore significantly
reducing test power.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-75&engl=0}
}
@inproceedings {INPROC-2005-128,
author = {Jun Zhou and Hans-Joachim Wunderlich},
title = {{Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschr{\"a}nkung}},
booktitle = {INFORMATIK 2005 - Informatik LIVE! Band 1, Beitr{\"a}ge der 35. Jahrestagung der Gesellschaft f{\"u}r Informatik e.V. (GI), Bonn, 19. bis 22. September 2005},
editor = {Armin B. Cremers and Rainer Manthey and Peter Martini and Volker Steinhage},
address = {Bonn},
publisher = {K{\"o}llen Druck+Verlag GmbH},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {Lecture Notes in Informatics},
volume = {P-67},
pages = {441--441},
type = {Konferenz-Beitrag},
month = {September},
year = {2005},
isbn = {3-88579-396-2},
issn = {1617-5468},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-128&engl=0}
}
@inproceedings {INPROC-2005-118,
author = {Patrick Jaeger and Bernd Bertsche and Talal Arnout and Hans-Joachim Wunderlich},
title = {{Fr{\"u}he Zuverl{\"a}ssigkeitsanalyse mechatronischer Systeme}},
booktitle = {VDI Berichte 1884, 22. VDI Tagung Technische Zuverl{\"a}ssigkeit (TTZ'05); Stuttgart; April 7-8, 2005},
address = {D{\"u}sseldorf},
publisher = {VDI Verlag},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {39--56},
type = {Konferenz-Beitrag},
month = {April},
year = {2005},
language = {Deutsch},
cr-category = {A General Literature},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Mechatronische Systeme sind heutzutage allgegenw{\"a}rtig. Durch die Kombination
aus Mechanik und moderner Informationsverarbeitung (Elektronik und Software)
kann die Leistungsf{\"a}higkeit von Produkten deutlich gesteigert werden. Ein
Beispiel hierf{\"u}r sind CVTGetriebe. Die ersten Getriebe dieser Bauart waren
weitgehend mechanisch/hydraulische Strukturen [1]. Modernere CVT-Getriebe, wie
das ZF Ecotronic [2] oder das Front-CVT der Mercedes-Benz A-Klasse [3] verf{\"u}gen
{\"u}ber eine elektronische Steuerung, die die Leistungsf{\"a}higkeit des Getriebes zu
steigern vermag aber auch zu UnZuverl{\"a}ssigkeiten f{\"u}hren kann. In diesem Beitrag
soll das Thema der Zuverl{\"a}ssigkeit mechatronischer Systeme aufgegriffen werden
und insbesondere vor dem Hintergrund der Zuverl{\"a}ssigkeitsarbeit in Fr{\"u}hen
Entwicklungsphasen diskutiert werden, da namentlich die Konzeptphase durch die
Auswahl des richtigen Konzeptes f{\"u}r den endg{\"u}ltigen Produkterfolg
hauptverantwortlich ist. Hierzu wird speziell das Thema der
Informationsgewinnung in Fr{\"u}hen Phasen thematisiert, da der Erfolg der
Zuverl{\"a}ssigkeitsarbeit ma{\ss}geblich von der Daten- und Informationslage abh{\"a}ngig
ist.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-118&engl=0}
}
@inproceedings {INPROC-2005-117,
author = {Abdul Wahid Hakmi and Hans-Joachim Wunderlich and Valentin Gherman and Michael Garbers and Juergen Schloeffel},
title = {{Implementing a Scheme for External Deterministic Self-Test}},
booktitle = {Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS'05); Palm Springs, CA, USA; May 1-5, 2005},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2314},
pages = {101--106},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2005},
isbn = {0-7695-2314-5},
issn = {1093-0167},
doi = {10.1109/VTS.2005.50},
keywords = {deterministic self-test; external BIST; test resource partitioning; test data compression},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {A method for test resource partitioning is introduced which keeps the
design-for-test logic test set independent and moves the test pattern dependent
information to an external, programmable chip. The scheme includes a new
decompression scheme for a fast and efficient communication between the
external test chip and the circuit under test. The hardware costs on chip are
significantly lower compared with a deterministic BIST scheme while the test
application time is still in the same range. The proposed scheme is fully
programmable, flexible and can be reused at board level for testing in the
field. Keywords: Deterministic self-test, external BIST, test resource
partitioning, test data compression.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-117&engl=0}
}
@inproceedings {INPROC-2005-116,
author = {Piet Engelke and Valentin Gherman and Ilia Polian and Yuyi Tang and Hans-Joachim Wunderlich and Bernd Becker},
title = {{Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST}},
booktitle = {Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS); Sopron, Hungary; April 13-16, 2005},
publisher = {Institute of Electrical and Electronics Engineers, Inc.},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {11--18},
type = {Konferenz-Beitrag},
month = {April},
year = {2005},
keywords = {Test Tradeoffs; Logic BIST; Defect Coverage; Resistive Bridging Faults},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {For the first time, we study the coverage of non-target defects for
Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST
implementation options that result in test sequences of different lengths.
Resistive bridging faults are used as a surrogate of non-target defects.
Experimental data obtained for largest ISCAS benchmarks suggests that, although
DLBIST always guarantees complete stuck-at coverage, test sequence length does
influence the non-target defect detection capabilities. For circuits with a
large fraction of random-pattern resistant faults, the embedded deterministic
patterns as well as a sufficient amount of random patterns are both
demonstrated to be essential for non-target defect detection. It turns out,
moreover, that area cost is lower for DLBIST solutions with longer test
sequences, due to additional degrees of freedom for the embedding procedure and
a lower number of faults undetected by pseudorandom patterns. This implies that
DLBIST is particularly effective in covering non-target defects.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-116&engl=0}
}
@inproceedings {INPROC-2005-115,
author = {Hans-Joachim Wunderlich},
title = {{From Embedded Test to Embedded Diagnosis}},
booktitle = {Proceedings of the 10th IEEE European Test Sypmposium (ETS'05); Tallinn, Estonia; May 22-25, 2005},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {P2341},
pages = {216--221},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2005},
isbn = {0-7695-2341-2},
issn = {1530-1877},
doi = {10.1109/ETS.2005.26},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Testing integrated circuits with millions of transistors puts strong
requirements on test volume, test application time, test speed, and test
resolution. To overcome these challenges, it is widely accepted to partition
test resources between the automatic test equipment (ATE) and the circuit under
test (CUT). These strategies may reach from simple test data
compression/decompression schemes to implementing a complete built-in
self-test. Very often these schemes come with reduced diagnostic resolution. In
this paper, an overview is given on techniques for embedding test into a
circuit while still keeping diagnostic capabilities. Built-in diagnosis
techniques may be used after manufacturing, for chip characterization and field
return analysis, and even for rapid prototyping.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-115&engl=0}
}
@inproceedings {INPROC-2005-114,
author = {Kiatisevi Pattara and Luis Azuara and Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Development of an Audio Player as System-on-a-Chip using an Open Source Platform}},
booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, Vol. 3, May 23-26, 2005},
publisher = {Institute of Electrical and Electronics Engineers, Inc.},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {2935--2938},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2005},
isbn = {0-7803-8834-8},
doi = {10.1109/ISCAS.2005.1465242},
language = {Englisch},
cr-category = {B.0 Hardware General,
D.0 Software General},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Open source software are becoming more widely-used, notably in the server and
desktop applications. For embedded systems development, usage of open source
software can also reduce development and licensing costs. We report on our
experience in developing a Systemon- a-Chip (SoC) audio player using various
open source components in both hardware and software parts as well as in the
development process. The Ogg Vorbis audio decoder targeted for limited
computing resource and low power consumption devices was developed on the free
LEON SoC platform, which features SPARC-V8 architecture compatible processor
and AMBA bus. The decoder runs on the open source RTEMS operating system making
use of the royalty-free open source Vorbis library. We also aim to illustrate
the use of hardware/software co-design techniques. Therefore, in order to speed
up the decoding process, after an analysis, a computing-intensive part of the
decoding algorithm was selected and designed as an AMBA compatible hardware
core. The demonstration prototype was built on the XESS XSV-800 prototyping
board using GNU/Linux workstations as development workstations. This project
shows that development of SoC using open source platform is viable and might be
the preferred choice in the future.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-114&engl=0}
}
@inproceedings {INPROC-2005-113,
author = {Oliver H{\'e}ron and Talal Arnaout and Hans-Joachim Wunderlich},
title = {{On the Reliability Evaluation of SRAM-based FPGA Designs}},
booktitle = {Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
editor = {IEEE Computer Society},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {05EX1155},
pages = {403--408},
type = {Konferenz-Beitrag},
month = {August},
year = {2005},
isbn = {0-7803-9362-7},
doi = {10.1109/FPL.2005.1515755},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of
use ranging from consumer products to astronautics. This diversity necessitates
the need to evaluate the reliability of the FPGA, because of their high
susceptibility to soft errors, which are due to the high density of embedded
SRAM cells. Reliability evaluation is an important step in designing highly
reliable systems, which results in a strong competitive advantage in today's
marketplace. This paper proposes a mathematical model able to evaluate and
therefore help to improve the reliability of SRAM-based FPGAs.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-113&engl=0}
}
@inproceedings {INPROC-2004-87,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Harald Vranken and Friedrich Hapke and Michael Wittke},
title = {{Efficient Pattern Mapping For Deterministic Logic BIST}},
booktitle = {Proceedings of the 9th IEEE European Test Sypmposium (ETS'04); Ajaccio, Corsica, France; May 23-26, 2004},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society Conference Publishing Services},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {Informal track},
pages = {327--332},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2004},
keywords = {Logic BIST; BDDs},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Deterministic logic BIST (DLBIST) is an attractive test strategy, since it
combines advantages of deterministic external testing and pseudo-random LBIST.
Unfortunately, previously published DLBIST methods are unsuited for large ICs,
since the computing time and memory consumption of the DLBIST synthesis
algorithms increases expotentially, or at least cubically, with the circuit
size. In this paper, we propose a novel DLBIST synthesis procedure that has
nearly linear complexity in terms of both computing time and memory
consumption. The new algorithms are based on binary decision diagrams (BDDs).
We demonstrate the efficiency of the new algorithms for industrial designs up
to 4M gates.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2004-87&engl=0}
}
@inproceedings {INPROC-2004-82,
author = {Harald Vranken and Ferry Syafei Sapei and Hans-Joachim Wunderlich},
title = {{Impact of Test Point Insertion on Silicon Area and Timing during Layout}},
booktitle = {Proceedings of the 7th Conference on Design, Automation and Test in Europe (DATE'04); Paris, France; February 16-20, 2004, Vol. 2},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {PR02085},
pages = {810--815},
type = {Konferenz-Beitrag},
month = {Februar},
year = {2004},
isbn = {0-7695-2085-5},
issn = {1530-1591},
doi = {10.1109/DATE.2004.1268981},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {This paper presents an experimental investigation on the impact of test point
insertion on circuit size and performance. Often test points are inserted into
a circuit in order to improve the circuit's testability, which results in
smaller test data volume, shorter test time, and higher fault coverage.
Inserting test points however requires additional silicon area and influences
the timing of a circuit. The paper shows how placement and routing is affected
by test point insertion during layout generation. Experimental data for
industrial circuits show that inserting 1\% test points in general increases the
silicon area after layout by less than 0.5\% while the performance of the
circuit may be reduced by 5\% or more.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2004-82&engl=0}
}
@inproceedings {INPROC-2004-81,
author = {Peter Goehner and Eduard Zimmer and Talal Arnaout and Hans-Joachim Wunderlich},
title = {{Reliability Considerations for Mechatronic Systems on the Basis of a State Model}},
booktitle = {Proc. of the 17th International Conference on Architecture of Computing Systems (ARCS'04); Augsburg, Germany; March 23-26, 2004},
address = {Bonn},
publisher = {Gesellschaft f{\"u}r Informatik},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {106--112},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2004},
isbn = {3-88579-370-9},
language = {Englisch},
cr-category = {A General Literature},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The first step in analyzing a problem is to establish a valid model that would
represent this problem. The model helps mainly in understanding the problem by
depicting it in a visual form. Hence, in order to analyze the reliability of
mechatronic systems, we need to understand first how such systems fail and how
they behave in the presence of a failure. This understanding would help us
later in the analysis and the development of formal solutions to achieve the
demanded reliability. This could be achieved using the model that we have
developed, which will be presented in this paper.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2004-81&engl=0}
}
@inproceedings {INPROC-2004-80,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Harald Vranken and Friedrich Hapke and Michael Wittke and Michael Garbers},
title = {{Efficient Pattern Mapping For Deterministic Logic BIST}},
booktitle = {Proceedings of the 35th IEEE International Test Conference (ITC'04); Charlotte, NC, USA, October 25-28; 2004},
editor = {International Test Conference},
address = {Washington, D.C.},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {04CH37586},
pages = {48--56},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2004},
isbn = {0-7803-8580-2},
issn = {1089-3539},
isbn = {ieee: 1386936},
keywords = {Logic BIST; BDDs},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?&arnumber=1386936},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Deterministic logic BIST (DLBIST) is an attractive test strategy, since it
combines advantages of deterministic external testing and pseudo-random LBIST.
Unfortunately, previously published DLBIST methods are unsuited for large ICs,
since computing time and memory consumption of the DLBIST synthesis algorithms
increase exponentially, or at least cubically, with the circuit size. In this
paper, we propose a novel DLBIST synthesis procedure that has nearly linear
complexity in terms of both computing time and memory consumption. The new
algorithms are based on binary decision diagrams (BDDs). We demonstrate the
efficiency of the new algorithms for industrial designs up to 2M gates.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2004-80&engl=0}
}
@inproceedings {INPROC-2004-79,
author = {Yuyi Tang and Hans-Joachim Wunderlich and Harald Vranken and Friedrich Hapke and Michael Wittke and Piet Engelke and Ilian Polian and Bernd Becker},
title = {{X-Masking During Logic BIST and Its Impact on Defect Coverage}},
booktitle = {Proceedings of the 35th IEEE International Test Conference (ITC'04), Charlotte, NC, USA; October 25-28; 2004},
editor = {International Test Conference},
address = {Washington, D.C.},
publisher = {IEEE Xplore},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Catalog Number},
volume = {04CH37586},
pages = {442--451},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2004},
isbn = {0-7803-8580-2},
issn = {1089-3539},
doi = {10.1109/TEST.2004.1386980},
keywords = {X-Masking; Logic BIST; Defect Coverage; Resistive Bridging Faults},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {We present a technique for making a circuit ready for Logic BIST by masking
unknown values at its outputs. In order to keep the area overhead low, some
known bits in output responses are also allowed to be masked. These bits are
selected based on a stuck-at n-detection based metric, such that the impact of
masking on the defect coverage is minimal. An analysis based on a probabilistic
model for resistive short defects indicates that the coverage loss for
unmodeled defects is negligible for relatively low values of n.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2004-79&engl=0}
}
@inproceedings {INPROC-2003-56,
author = {Yves Bertrand and Marie-Lise Flottes and Luz Balado and Joan Figueras and Anton Biasizzo and Frank Novak and Stefano di Carlo and Paolo Prinetto and Nicoleta Pricopi and Hans-Joachim Wunderlich},
title = {{Test Engineering Education in Europe: the EuNICE-Test Project}},
booktitle = {Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE'03); Anaheim, CA; June 1-2, 2003},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
series = {IEEE Computer Society Order Number},
volume = {PR01973},
pages = {85--86},
type = {Konferenz-Beitrag},
month = {Juni},
year = {2003},
isbn = {0-7695-1973-3},
doi = {10.1109/MSE.2003.1205266},
language = {Englisch},
cr-category = {A General Literature},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The paper deals with a European experience of education in industrial test of
ICs and SoCs using remote testing facilities. The project addresses the problem
of the shortage in microelectronics engineers aware with the new challenge of
testing mixed-signal SoCs for multimedia/telecom market. It aims at providing
test training facilities at a European scale in both initial and continuing
education contexts. This is done by allowing the academic and industrial
partners of the consortium to train engineers using the common test resources
center (CRTC) hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de
Micro-{\'e}lectronique de Montpellier, France). CRTC test tools include
up-to-date/high-tech testers that are fully representative of real industrial
testers as used on production testfloors. At the end of the project, it is
aimed at reaching a cruising speed of about 16 trainees per year per center.
Each trainee will have attend at least one one-week training using the remote
test facilities of CRTC.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2003-56&engl=0}
}
@inproceedings {INPROC-2002-47,
author = {Arnaud Virazel and Hans-Joachim Wunderlich},
title = {{Power Conscious BIST Approaches}},
booktitle = {3. VIVA Schwerpunkt-Kolloquium; Chemnitz, Germany; 18. - 19. March 2002},
publisher = {-},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {128--135},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2002},
isbn = {3-00-008 995-0},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The System-On-Chip (SOC) revolution has brought some new challenges to both
design and test engineers. The most important challenges of today’s VLSI
systems testing are linked to test cost, defect coverage and power dissipation.
Implementing a self-testable system may reduce test costs as expensive external
high performance test equipment is not required and it may increase defect
coverage as testing is performed at system speed. Unfortunately, the classic
BIST approaches lead to a significant increase of power consumption compared to
the system mode and even compared to external testing. The paper will review
required changes to be applied to classic BIST techniques for power reduction.
A recently developed new BIST approach called functional BIST is introduced and
its consequences for power dissipation are discussed.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-47&engl=0}
}
@inproceedings {INPROC-2002-45,
author = {Lars Schaefer and Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{RESPIN++ - Deterministic Embedded Test}},
booktitle = {Proceedings of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {139--146},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2002},
isbn = {0-7695-1715-3},
issn = {1530-1877},
doi = {10.1109/ETW.2002.1029637},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {RESPIN++ is a deterministic embedded test method tailored to system chips,
which implement scan test at core level. The scan chains of one core of the
system-on-a-chip are reused to decompress the patterns for another core. To
implement the RESPIN++ test architecture only a few gates need to be added to
the test wrapper. This will not affect the critical paths of the system. The
RESPIN++ method reduces both test data volume and test application time up to
one order of magnitude per core compared to storing compacted test patterns on
the ATE. If several cores may be tested concurrently, test data volume and test
application time for the complete system test may be reduced even further. This
paper presents the RESPIN++ test architecture and a compression algorithm for
the architecture.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-45&engl=0}
}
@inproceedings {INPROC-2002-44,
author = {Harald Vranken and Florian Meister and Hans-Joachim Wunderlich},
title = {{Combining Deterministic Logic BIST with Test Point Insertion}},
booktitle = {Proceedings of the 7th European Test Workshop (ETW'02); Korfu, Greece; May 26-29, 2002},
editor = {IEEE Computer Society},
address = {Los Alamitos, California},
publisher = {IEEE Computer Society},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
series = {IEEE Computer Society Order Number},
volume = {PR01715},
pages = {105--110},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2002},
isbn = {0-7695-1715-3},
issn = {1530-1877},
doi = {10.1109/ETW.2002.1029646},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents a logic BIST approach which combines deterministic logic
BIST with test point insertion. Test points are inserted to obtain a first
testability improvement, and next a deterministic pattern generator is added to
increase the fault efficiency up to 100\%. The silicon cell area for the
combined approach is smaller than for approaches that apply a deterministic
pattern generator or test points only. The combined approach also removes the
classical limitations and drawbacks of test point insertion, such as failing to
achieve complete fault coverage and a complicated design flow. The benefits of
the combined approach are demonstrated in experimental results on a large
number of ISCAS and industrial circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-44&engl=0}
}
@inproceedings {INPROC-2002-43,
author = {Rainer Dorsch and Ram{\'o}n Huerta Rivera and Hans-Joachim Wunderlich and Martin Fischer},
title = {{Adapting a SoC to ATE Concurrent Test Capabilities}},
booktitle = {Proceedings of the 33rd International Test Conference (ITC), Baltimore, MD, October 8-10, 2002},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
pages = {1169--1175},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2002},
isbn = {0-7803-7542-4},
isbn = {ISSN 1089-3539},
doi = {10.1109/TEST.2002.1041875},
keywords = {ATE; concurrent test; SoC test; test resource partitioning},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Concurrent test features are available in the next generation SoC testers to
increase ATE throughput. To exploit these new features design modifications are
necessary. In a case study, these modifications were applied to the open source
Leon SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several
embedded cores. The concurrent test of Leon was performed on an SoC tester. The
gain in test application time and area costs are quantified and obstacles in
the design flow for concurrent test are discussed.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-43&engl=0}
}
@inproceedings {INPROC-2001-82,
author = {Silvia Chiusano and Stefano di Carlo and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{On Applying the Set Covering Model to Reseeding}},
booktitle = {Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {156--160},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2001},
isbn = {0-7695-0993-2},
issn = {1530-1591},
doi = {10.1109/DATE.2001.915017},
keywords = {built-in self test; computational complexity; encoding; integrated circuit testing},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The Functional BIST approach is a rather new BIST technique based on exploiting
embedded system functionality to generate deterministic test patterns during
BIST. The approach takes advantages of two well-known testing techniques, the
arithmetic BIST approach and the reseeding method. The main contribution of the
present paper consists in formulating the problem of an optimal reseeding
computation as an instance of the set covering problem. The proposed approach
guarantees high flexibility, is applicable to different functional modules,
and, in general, provides a more efficient test set encoding then previous
techniques. In addition, the approach shorts the computation time and allows to
better exploiting the tradeoff between area overhead and global test length as
well as to deal with larger circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-82&engl=0}
}
@inproceedings {INPROC-2001-78,
author = {Alexander Irion and Gundolf Kiefer and Harald Vranken and Hans-Joachim Wunderlich},
title = {{Circuit Partitioning for Efficient Logic BIST Synthesis}},
booktitle = {Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE'01), Munich, Germany, March 12-16, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {86--91},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2001},
isbn = {0-7695-0993-2},
doi = {10.1109/DATE.2001.915005},
keywords = {circuit partitionig; deterministic BIST; divide-and-conquer},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A divide-and-conquer approach using circuit partitioning is presented, which
can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis
algorithms contain steps with a time complexity which increases more than
linearly with the circuit size. By extracting sub-circuits which are almost
constant in size, BIST synthesis for very large designs may be possible within
linear time. The partitioning approach does not require any physical
modifications of the circuit under test. Experiments show that significant
performance improvements can be obtained at the cost of a longer test
application time or a slight increase in silicon area for the BIST hardware.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-78&engl=0}
}
@inproceedings {INPROC-2001-77,
author = {Patrick Girard and Lois Guiller and Christian Landrault and Serge Pravossoudovitch and Hans-Joachim Wunderlich},
title = {{A Modified Clock Scheme for a Low Power BIST Test Pattern Generator}},
booktitle = {Proceedings of the 19th VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {306--311},
type = {Konferenz-Beitrag},
month = {April},
year = {2001},
isbn = {0-7695-1122-8},
issn = {1093-0167},
doi = {10.1109/VTS.2001.923454},
keywords = {Parallel BIST; Low-power Design; Test \& Low Power; Low Power BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper, we present a new low power BIST test pattern generator that
provides test vectors which can reduce the switching activity during test
operation. The proposed low power/energy BIST technique is based on a modified
clock scheme for the TPG and the clock tree feeding the TPG. Numerous
advantages can be found in applying such a technique. The fault coverage and
the test time are roughly the same as those achieved using a standard BIST
scheme. The area overhead is nearly negligible and there is no penalty on the
circuit delay. The proposed BIST scheme does not require any circuit design
modification beyond the parallel BIST technique, is easily implemented and has
low impact on the design time. It has been implemented based on an LFSR-based
TPG, but can also be designed using a cellular automata. Reductions of the
energy, average power and peak power consumption during test operation are up
to 94\%, 55\% and 48\% respectively for ISCAS and MCNC benchmark circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-77&engl=0}
}
@inproceedings {INPROC-2001-75,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Reusing Scan Chains for Test Pattern Decompression}},
booktitle = {Proceedings of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {124--132},
type = {Konferenz-Beitrag},
month = {Mai},
year = {2001},
isbn = {0-7695-10 16-7},
issn = {1530-1877},
keywords = {system-on-a-chip; embedded test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a method for testing a system-on-a-chip by using a
compressed representation of the patterns on an external tester. The patterns
for a certain core under test are decompressed by reusing scan chains of cores
idle during that time. The method only requires a few additional gates in the
wrapper, while the mission logic is untouched. Storage and bandwidth
requirements for the ATE are reduced significantly.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-75&engl=0}
}
@inproceedings {INPROC-2001-74,
author = {Hua-Guo Liang and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST}},
booktitle = {``Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {894--902},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
issn = {1089-3539},
doi = {10.1109/TEST.2001.966712},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel architecture for scan-based mixed mode BIST is presented.
To reduce the storage requirements for the deterministic patterns it relies on
a two-dimensional compression scheme, which combines the advantages of known
vertical and hoizontal compression techniques. To reduce both the number of
patterns to be stored and the number of bits to be stored for each pattern,
deterministic test cubes are encoded as seeds of an LFSR (horizontal
compression), and the seeds are again compressed into seeds of a folding
counter sequence (vertical compression). The proposed BIST architecture is
fully compatible with standard scan esign, simple and flexible, so that sharing
between several logic cores is p0ossible. Experimental results show that the
proposed scheme requires less test data storage than previously publiched
approaches providing the same flexibility and scan compatibility.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-74&engl=0}
}
@inproceedings {INPROC-2001-73,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Tailoring ATPG for Embedded Testing}},
booktitle = {Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {530--537},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
issn = {1089-3539},
doi = {10.1109/TEST.2001.966671},
keywords = {Test Resource Partitioning; Systems-on-a-Chip; ATPG},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An automatic test pattern generation (ATPG) method is presented Testability for
a scan-based test architecture which min-imizes ATE storage requirements and
reduces the bandwidth be-tween the automatic test equipment (ATE) and the chip
under test. To generate tailored deterministic test patterns, a standard ATPG
tool performing dynamic compaction and allowing constraints on circuit inputs
is used. The combination of an appropriate test ar-chitecture and the tailored
test patterns reduces the test data vol-ume up to two orders of magnitude
compared with standard com-pacted test sets.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-73&engl=0}
}
@inproceedings {INPROC-2001-72,
author = {Michael Kessler and Gundolf Kiefer and Jens Leenstra and Knut Schuenemann and Thomas Schwarz and Hans-Joachim Wunderlich},
title = {{Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability}},
booktitle = {Proceedings of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {461--469},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
issn = {1089-3539},
doi = {10.1109/TEST.2001.966663},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel hierarchical DfT methodology is presented which is
targeted to improve the delay fault testability for external testing and
scan-based BIST. After the partitioning of the design into high frequency
macros, the analysis for delay fault testability already starts in parallel
with the implementation at the macro level. A specification is generated for
each macro that defines the delay fault testing characteristics at the macro
boundaries. This specification is used to analyse and improve the delay fault
testability by improving the scan chain ordering at macro-level before the
macros are connected together into the total chip network. The hierarchical
methodology has been evaluated with the instruction window buffer core of an
out-of-order processor. It was shown that for this design practically no extra
hardware is required.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-72&engl=0}
}
@inproceedings {INPROC-2001-42,
author = {Michael Kessler and Gundolf Kiefer and Jens Leenstra and Knut Sch{\"u}nemann and Thomas Schwarz and Hans-Joachim Wunderlich},
title = {{Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability}},
booktitle = {Proceedings of the International Test Conference : ITC 2001 ; Baltimore, Maryland, October 30-November 1, 2001},
publisher = {IEEE Computer Society Press},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {461--469},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2001},
isbn = {0-7803-7169-0},
keywords = {hierarchical; DfT; BIST; testability; scan chain reordering},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
C.1 Processor Architectures,
C.4 Performance of Systems},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Parallele und Verteilte H{\"o}chstleistungsrechner, Anwendersoftware;
Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel hierarchical DfT methodology is presented which is
targeted to improve the delay fault testability for external testing and
scan-based BIST. After the partitioning of the design into high frequency
macros, the analysis for delay fault testability already starts in parallel
with the implementation at the macro level. A specification is generated for
each macro that defines the delay fault testing characteristics at the macro
boundaries. This specification is used to analyse and improve the delay fault
testability by improving the scan chain ordering at macro-level before the
macros are connected together into the total chip network. The hierarchical
methodology has been evaluated with the instruction window buffer core of an
out-of-order processor. It was shown that for this design practically no extra
hardware is required.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-42&engl=0}
}
@inproceedings {INPROC-2000-46,
author = {Silvia Cataldo and Silvia Chiusano and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{Optimal Hardware Pattern Generation for Functional BIST}},
booktitle = {Proceedings of the 3rd Conference on Design and Test in Europe (DATE), Paris, France, March 27-30, 2000},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {292--297},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {2000},
isbn = {0-7695-0537-6},
issn = {1530-1591},
doi = {10.1109/DATE.2000.840286},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Functional BIST is a promising solution for self-testing complex digital
systems at reduced costs in terms of area and performance degradation. The
present paper addresses the computation of optimal seeds for an arbitrary
sequential module to be used as hardware test pattern generator. Up to now,
only linear feedback shift registers and accumulator based structures have been
used for deterministic test pattern generation by reseeding. In this paper, a
method is proposed which can be applied to general finite state machines.
Nevertheless the method is absolutely general, for sake of comparison with
previous approaches, in this paper an accumulator based unit is assumed as
pattern generator module. Experiments prove the effectiveness of the approach
which outperforms previous results for accumulators, in terms of test size and
test time, without sacrifying the fault detection capability.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-46&engl=0}
}
@inproceedings {INPROC-2000-45,
author = {Gundolf Kiefer and Harald Vranken and Erik Jan Marinessen and Hans-Joachim Wunderlich},
title = {{Application of Deterministic Logic BIST on Industrial Circuits}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 200},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {105--114},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894197},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {We present the application of a deterministic logic BIST scheme on
state-of-the-art industrial circuits. Experimental results show that complete
fault coverage can be achieved for industrial circuits up to 100K gates with
10,000 test patterns, at a total area cost for BIST hardware of typically
5\%-15\%. It is demonstrated that a trade-off is possible between test quality,
test time, and silicon area. In contrast to BIST schemes based on test point
insertion no modifications of the circuit under test are required, complete
fault efficiency is guaranteed, and the impact on the design process is
minimized.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-45&engl=0}
}
@inproceedings {INPROC-2000-44,
author = {Silvia Chiusano and Paolo Prinetto and Hans-Joachim Wunderlich},
title = {{Non-Intrusive BIST for Systems-on-a-Chip}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {644--651},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894259},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The term functional BIST describes a test method to control functional modules
so that they generate a deterministic test set, which targets structural faults
within other parts of the system. It is a promising solution for self-testing
complex digital systems at reduced costs in terms of area overhead and
performance degradation. While previous work mainly investigated the use of
functional modules for generating pseudo-random and pseudo-exhaustive test
patterns, the present paper shows that a variety of modules can also be used as
a deterministic test pattern generator via an appropriate reseeding strategy.
This method enables a BIST technique that does not introduce additional
hardware like test points and test registers into combinational and pipelined
modules under test. The experimental results prove that the reseeding method
works for accumulator based structures, multipliers, or encryption modules as
efficiently as for the classic linear feedback shift registers, and some times
even better.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-44&engl=0}
}
@inproceedings {INPROC-2000-43,
author = {Sybille Hellebrand and Hua-Guo Liang and Hans-Joachim Wunderlich},
title = {{A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters}},
booktitle = {Proceedings of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {778--784},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {2000},
isbn = {0-7803-6546-1},
issn = {1089-3539},
doi = {10.1109/TEST.2000.894274},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a
programmable Johnson counter and is called folding counter. Both the
theoretical background and practical algorithms are presented to characterize a
set of deterministic test cubes by a reasonably small number of seeds for a
folding counter. Combined with classical techniques for test width compression
and with pseudo-random pattern generation these new techniques provide an
efficient and flexible solution for scan-based BIST.. Experimental results show
that the proposed scheme outperforms previously published approaches based on
the reseeding of LFSRs or Johnson counters.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-43&engl=0}
}
@inproceedings {INPROC-1999-53,
author = {Vyacheslav N. Yarmolik and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Symmetric Transparent BIST for RAMs}},
booktitle = {Proceedings of the 2nd Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 9-12, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {702--708},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {1999},
isbn = {0-7695-0078-1},
doi = {10.1109/DATE.1999.761206},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper introduces the new concept of symmetric transparent BIST for RAMs.
This concept allows to skip the signature prediction phase of conventional
transparent BIST approaches and therefore yields a significant reduction of
test time. The hardware cost and the fault coverage of the new scheme remain
comparable to that of a traditional transparent BIST scheme. In many cases,
experimental studies even show a higher fault coverage obtained in shorter test
time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-53&engl=0}
}
@inproceedings {INPROC-1999-52,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Alexander Ivaniuk and Yuri Klimets and Vyacheslav N. Yarmolik},
title = {{Error Detecting Refreshment for Embedded DRAMs}},
booktitle = {Proceedings of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 25-29, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {384--390},
type = {Konferenz-Beitrag},
month = {April},
year = {1999},
isbn = {0-7695-0146-X},
issn = {1093-0167},
doi = {10.1109/VTEST.1999.766693},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents a new technique for on-line consistency checking of
embedded DRAMs. The basic idea is to use the refresh cycle for concurrently
computing a test characteristic of the memory contents and compare it to a
precomputed reference characteristic. Experiments show that the proposed
technique significantly reduces the time between the occurrence of an error and
its detection (error detection latency). It also achieves a very high error
coverage at low hardware costs. Therefore it perfectly complements standard
on-line checking approaches relying on error detecting codes, where the
detection of certain types of errors is guaranteed, but only during READ
operations accessing the erroneous data.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-52&engl=0}
}
@inproceedings {INPROC-1999-51,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Partial Scan}},
booktitle = {Proceedings of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {110--117},
type = {Konferenz-Beitrag},
month = {Mai},
year = {1999},
isbn = {0-7695-0390-X},
doi = {10.1109/ETW.1999.804415},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An efficient deterministic BIST scheme based on partial scan chains together
with a scan selection algorithm tailored for BIST is presented. The algorithm
determines a minimum number of flipflops to be scannable so that the remaining
circuit has a pipeline-like structure. Experiments show that scanning less
flipflops may even decrease the hardware overhead for the on-chip pattern
generator besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-51&engl=0}
}
@inproceedings {INPROC-1999-50,
author = {Vyacheslav N. Yarmolik and I.V. Bykov and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms}},
booktitle = {Proceedings of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999},
address = {Berlin / Heidelberg},
publisher = {Springer},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {339--350},
type = {Konferenz-Beitrag},
month = {September},
year = {1999},
isbn = {978-3-540-66483-3},
isbn = {ISSN 0302-9743},
doi = {10.1007/3-540-48254-7_23},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a new approach to transparent BIST for word-oriented RAMs
which is based on the transformation of March transparent test algorithms to
the symmetric versions. This approach allows to skip the signature prediction
phase inherent to conventional transparent memory testing and therefore to
significantly reduce test time. The hardware overhead and fault coverage of the
new BIST scheme are comparable to the conventional transparent BIST structures.
Experimental results show that in many cases the proposed test techniques
achieve a higher fault coverage in shorter test time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-50&engl=0}
}
@inproceedings {INPROC-1999-49,
author = {Stefan Gerstendoerfer and Hans-Joachim Wunderlich},
title = {{Minimized Power Consumption for Scan-Based BIST}},
booktitle = {Proceedings of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {77--84},
type = {Konferenz-Beitrag},
month = {September},
year = {1999},
isbn = {0-7803-5753-1},
issn = {1089-3539},
doi = {10.1109/TEST.1999.805616},
keywords = {BIST; Low Power; Power consumption},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Power consumption of digital systems may increase significantly during testing.
In this paper, systems equipped with a scan-based built-in self-test like the
STUMPS architecture are analyzed, the modules and modes with the highest power
consumption are identified, and design modifications to reduce power
consumption are proposed. The design modifications include some gating logic
for masking the scan path activity during shifting, and the synthesis of
additional logic for suppressing random patterns which do not contribute to
increase the fault coverage. These design changes reduce power consumption
during BIST by several orders of magnitude, at very low cost in terms of area
and performance.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1999-49&engl=0}
}
@inproceedings {INPROC-1998-43,
author = {Vyacheslav N. Yarmolik and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs}},
booktitle = {Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE), Paris, France,February 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {173--179},
type = {Konferenz-Beitrag},
month = {Februar},
year = {1998},
isbn = {0-8 186-8359-7},
isbn = {},
doi = {10.1109/DATE.1998.655853},
keywords = {built-in self test; data compression; integrated circuit testing; random-access storage},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {After write operations, BIST schemes for RAMs relying on signature analysis
must compress the entire memory contents to update the reference signature.
This paper introduces a new scheme for output data compression which avoids
this overhead while retaining the benefits of signature analysis. The proposed
technique is based on a new memory characteristic derived as the modulo-2 sum
of all addresses pointing to non-zero cells. This characteristic can be
adjusted concurrently with write operations by simple EXOR-operations on the
initial characteristic and on the addresses affected by the change.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-43&engl=0}
}
@inproceedings {INPROC-1998-42,
author = {Andre Hertwig and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Fast Self-Recovering Controllers}},
booktitle = {Proceedings of the 16th IEEE VLSI Test Symposium (VTS), Monterey, CA, April 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {296--302},
type = {Konferenz-Beitrag},
month = {April},
year = {1998},
isbn = {0-8 186-8436-4},
issn = {1093-0167},
doi = {10.1109/VTEST.1998.670883},
keywords = {FSM synthesis; fault-tolerance; checkpointing; performance-driven synthesis},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A fast fault-tolerant controller structure is presented, which is capable of
recovering from transient faults by performing a rollback operation in
hardware.
The proposed fault-tolerant controller structure utilizes the rollback hardware
also for system mode and this way achieves performance improvements of more
than 50\% compared to controller structures made fault-tolerant by conventional
techniques, while the hardware overhead is often negligible. The proposed
approach is compatible with state-of-the-art methods for FSM decomposition,
state encoding and logic synthesis.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-42&engl=0}
}
@inproceedings {INPROC-1998-41,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Accumulator Based Deterministic BIST}},
booktitle = {Proceedings of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {412--421},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {1998},
isbn = {0-7803-5092-8},
issn = {1089-3539},
doi = {10.1109/TEST.1998.743181},
keywords = {BIST; hardware pattern generator; embedded cores},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Most built-in self test (BIST) solutions require specialized test pattern
generation hardware which may introduce significant area overhead and
performance degradation. Recently, some authors proposed test pattern
generation on chip by means of functional units also used in system mode like
adders or multipliers. These schemes generate pseudo-random or
pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under
test contains random pattern resistant faults a deterministic test pattern
generator is necessary to obtain complete fault coverage.
In this paper it is shown that a deterministic test set can be encoded as
initial values of an accumulator based structure, and all testable faults can
be detected within a given test length by carefully selecting the seeds of the
accumulator. A ROM is added for storing the seeds, and the control logic of the
accumulator is modified. In most cases the size of the ROM is less than the
size required by traditional LFSR-based reseeding approaches.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-41&engl=0}
}
@inproceedings {INPROC-1998-40,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Multiple Scan Chains}},
booktitle = {Proceedings of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {1057--1064},
type = {Konferenz-Beitrag},
month = {Oktober},
year = {1998},
isbn = {0-7803-5092-8},
issn = {1089-3539},
doi = {10.1109/TEST.1998.743304},
keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented.
A procedure is described for synthesizing a pattern generator which stimulates
all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach
while better or even complete fault coverage is obtained at the same time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-40&engl=0}
}
@inproceedings {INPROC-1998-39,
author = {Vyacheslav N. Yarmolik and Yuri Klimets and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{New Transparent RAM BIST Based on Self-Adjusting Output Data Compression}},
booktitle = {Proceedings of Design \& Diagnostics of Electronic Circuits \& Systems (DDECS), Szczyrk, Poland, September 1998},
address = {Gliwice},
publisher = {Silesian Techn. Univ. Press},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {27--33},
type = {Konferenz-Beitrag},
month = {September},
year = {1998},
isbn = {83-90840-96-0},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The new memory transparent BIST technique is proposed in this paper. It has
more higher fault coverage compare to classical transparent technique. Also
this technique decreases the test complexity up to 50\% for the most of march
tests.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-39&engl=0}
}
@inproceedings {INPROC-1998-38,
author = {Madhavi Karkal and Nur A. Touba and Hans-Joachim Wunderlich},
title = {{Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST}},
booktitle = {Proceedings of the 7th Asian Test Symposium (ATS), Singapore, December 2-4, 1998},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {492--499},
type = {Konferenz-Beitrag},
month = {Dezember},
year = {1998},
isbn = {0-8 186-8277-9},
issn = {1081-7735},
doi = {10.1109/ATS.1998.741662},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In mixed-mode BIST, deterministic test patterns are generated with on-chip
hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed
by the pseudo-random patterns. While previous work in mixed-mode BIST has
focussed on developing hardware schemes for more efficiently encoding a given
set of deterministic patterns (generated by a conventional ATPG procedure), the
approach taken in this paper is to improve the encoding efficiency (and hence
reduce hardware overhead) by specially selecting a set of deterministic
patterns for the r.p.r. faults that can be efficiently encoded. A special ATPG
procedure is described for finding test patterns for the r.p.r. faults that are
correlated (have the same logic value) in many bit positions. Such test
patterns can be efficiently encoded with one of the many ``bit-fixing'' schemes
that have been described in the literature. Results are shown for different
bit-fixing schemes which indicate dramatic reductions in BIST overhead can be
achieved by using the proposed ATPG procedure to select which test patterns to
encode.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1998-38&engl=0}
}
@inproceedings {INPROC-1997-32,
author = {Andre Hertwig and Hans-Joachim Wunderlich},
title = {{Fast Controllers for Data Dominated Applications}},
booktitle = {Proceedings of the European Design \& Test Conference (ED\&TC), Paris, France, March 1997},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {84--89},
type = {Konferenz-Beitrag},
month = {M{\"a}rz},
year = {1997},
isbn = {0-8186-7786-4},
isbn = {ISSN 1066-1409},
doi = {10.1109/EDTC.1997.582337},
keywords = {FSM synthesis, performance driven synthesis; synthesis of testable controllers},
language = {Englisch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A target structure for implementing fast edge-triggered control units is
presented. In many cases, the proposed controller is faster than a one-hot
encoded structure as its correct timing does not require master-slave
flip-flops even in the presence of unpredictable clocking skews. A synthesis
procedure is proposed which leads to a performance improvement of 40\% on
average for the standard benchmark set whereas the additional area is less than
25\% compared with conventional finite state machine (FSM) synthesis. The
proposed approach is compatible with the state-of-the-art methods for FSM
decomposition, state encoding and logic synthesis.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1997-32&engl=0}
}
@inproceedings {INPROC-1997-31,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Using BIST Conitrol for Pattern Generation}},
booktitle = {Proc. of the 28th IEEE International Test Conference (ITC), Washington, DC, November 1997},
publisher = {International Test Conference},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {347--355},
type = {Konferenz-Beitrag},
month = {November},
year = {1997},
isbn = {0-7803-4209-7},
issn = {1089-3539},
doi = {10.1109/TEST.1997.639636},
keywords = {deterministic BIST; scan-based BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme is presented which requires less hardware overhead
than pseudo-random BIST but obtains better or even complete fault coverage at
the same time. It takes advantage of the fact that any autonomous BIST scheme
needs a BIST control unit for indicating the completion of the self-test at
least.
Hence, pattern counters and bit counters are always available, and they provide
information to be used for deterministic pattern generation by some additional
circuitry. This paper presents a systematic way for synthesizing a pattern
generator which needs less area than a 32-bit LFSR for random pattern
generation for all the benchmark circuits.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1997-31&engl=0}
}
@inproceedings {INPROC-1996-22,
author = {Hans-Joachim Wunderlich and Gundolf Kiefer},
title = {{Bit-Flipping BIST}},
booktitle = {Proceedings of the ACM/IEEE International Conference on CAD-96 (ICCAD), San Jose, CA, November 1996},
publisher = {Institute of Electrical and Electronics Engineers},
institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Germany},
pages = {337--343},
type = {Konferenz-Beitrag},
month = {November},
year = {1996},
isbn = {0-8186-7597-7},
issn = {1063-6757},
doi = {10.1109/ICCAD.1996.569803},
keywords = {Mixed-Mode BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A scan-based BIST scheme is presented which guarantees complete fault coverage
with very low hardware overhead. A probabilistic analysis shows that the output
of an LFSR which feeds a scan path has to be modified only at a few bits in
order to transform the random patterns into a complete test set. These
modifications may be implemented by a bit-flipping function which has the
LFSR-state as an input, and flips the value shifted into the scan path at
certain times. A procedure is described for synthesizing the additional
bit-flipping circuitry, and the experimental results indicate that this
mixed-mode BIST scheme requires less hardware for complete fault coverage than
all the other scan-based BIST approaches published so far.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-1996-22&engl=0}
}
@article {ART-2010-12,
author = {Michael A. Kochte and Christian G. Zoellin and Hans-Joachim Wunderlich},
title = {{Efficient Concurrent Self-Test with Partially Specified Patterns}},
journal = {Journal of Electronic Testing: Theory and Applications (JETTA), 2010},
publisher = {Springer Netherlands},
volume = {26},
type = {Artikel in Zeitschrift},
month = {August},
year = {2010},
isbn = {0923-8174},
doi = {10.1007/s10836-010-5167-6},
keywords = {Concurrent self-test; BIST; Test generation; VLSI},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Structural on-line self-test may be performed to detect permanent faults and
avoid their accumulation in the system. This paper improves existing techniques
for concurrent BIST that are based on a deterministic test set. Here, the test
patterns are specially generated with a small number of specified bits. This
results in very low test length and fault detection latency, which allows to
frequently test critical faults. As a consequence, the likelihood of fault
accumulation is reduced. Experiments with benchmark circuits show that the
hardware overhead is significantly lower than the overhead of the state of the
art. Moreover, a case-study on a super-scalar RISC processor demonstrates the
feasibility of the method.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2010-12&engl=0}
}
@article {ART-2010-11,
author = {Claus Braun and Hans-Joachim Wunderlich},
title = {{Algorithmen-basierte Fehlertoleranz f{\"u}r Many-Core-Architekturen}},
journal = {it - Information Technology},
publisher = {Oldenbourg Wissenschaftsverlag},
volume = {52},
number = {4},
pages = {209--215},
type = {Artikel in Zeitschrift},
month = {August},
year = {2010},
issn = {1611-2776},
doi = {10.1524/itit.2010.0593},
keywords = {Zuverl{\"a}ssigkeit; Fehlertoleranz; parallele Architekturen; parallele Programmierung},
language = {Deutsch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance,
C.1.4 Processor Architectures, Parallel Architectures,
C.4 Performance of Systems,
D.1.3 Concurrent Programming},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Moderne Many-Core-Architekturen bieten ein sehr hohes Potenzial an
Rechenleistung. Dies macht sie besonders f{\"u}r Anwendungen aus dem Bereich des
wissenschaftlichen Hochleistungsrechnens und der Simulationstechnik attraktiv.
Die Architekturen folgen dabei einem Ausf{\"u}hrungsparadigma, das sich am besten
durch den Begriff “Many-Threading” beschreiben l{\"a}sst. Wie alle
nanoelektronischen Halbleiterschaltungen leiden auch Many-Core-Prozessoren
potentiell unter st{\"o}renden Einfl{\"u}ssen von transienten Fehlern (soft errors) und
diversen Arten von Variationen. Diese Faktoren k{\"o}nnen die Zuverl{\"a}ssigkeit von
Systemen negativ beeinflussen und erfordern Fehlertoleranz auf allen Ebenen,
von der Hardware bis zur Software. Auf der Softwareseite stellt die
Algorithmen-basierte Fehlertoleranz (ABFT) eine ausgereifte Technik zur
Verbesserung der Zuverl{\"a}ssigkeit dar. Der Aufwand f{\"u}r die Anpassung dieser
Technik an moderne Many-Threading-Architekturen darf jedoch keinesfalls
untersch{\"a}tzt werden. In diesem Beitrag wird eine effiziente und fehlertolerante
Abbildung der Matrixmultiplikation auf eine moderne Many-Core-Architektur
pr{\"a}sentiert. Die Fehlertoleranz ist dabei integraler Bestandteil der Abbildung
und wird durch ein ABFT-Schema realisiert, das die Leistung nur unwesentlich
beeintr{\"a}chtigt.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2010-11&engl=0}
}
@article {ART-2009-23,
author = {Stefan Holst and Hans-Joachim Wunderlich},
title = {{Adaptive Debug and Diagnosis Without Fault Dictionaries}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA); August 2009},
publisher = {Springer Netherlands},
volume = {25},
number = {4-5},
pages = {259--268},
type = {Artikel in Zeitschrift},
month = {August},
year = {2009},
issn = {0923-8174},
doi = {10.1007/s10836-009-5109-3},
keywords = {Diagnosis; Debug; Test; VLSI},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Diagnosis is essential in modern chip production to increase yield, and debug
constitutes a major part in the pre-silicon development process. For recent
process technologies, defect mechanisms are increasingly complex, and
continuous efforts are made to model these defects by using sophisticated fault
models. Traditional static approaches for debug and diagnosis with a simplified
fault model are more and more limited. In this paper, a method is presented,
which identifies possible faulty regions in a combinational circuit, based on
its input/output behavior and independent of a fault model. The new adaptive,
statistical approach is named POINTER for 'Partially Overlapping Impact
couNTER' and combines a flexible and powerful effect-cause pattern analysis
algorithm with high-resolution ATPG. We show the effectiveness of the approach
through experiments with benchmark and industrial circuits. In addition, even
without additional patterns this analysis method provides good resolution for
volume diagnosis, too.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2009-23&engl=0}
}
@article {ART-2007-23,
author = {Hans-Joachim Wunderlich and Melani Elm and Stefan Holst},
title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip}},
journal = {Informacije MIDEM; Bled, Slovenia},
address = {Ljubljana},
publisher = {MIDEM},
volume = {37(4},
number = {124)},
pages = {235--243},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {2007},
issn = {0352-9045},
keywords = {Diagnosis; Debug; Embedded Test},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Rising design complexity and shrinking structures pose new challenges for debug
and diagnosis. Finding bugs and defects quickly during the whole life cycle of
a product is crucial for time to market, time to volume and improved product
quality. Debug of design errors and diagnosis of defects have many common
aspects. In this paper we give an overview of state of the art algorithms,
which tackle both tasks, and present an adaptive approach to design debug and
logic diagnosis.
Special design for diagnosis is needed to maintain visibility of internal
states and diagnosability of deeply embedded cores. This article discusses
current approaches to design for diagnosis to support all debug tasks from
first silicon to the system level.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-23&engl=0}
}
@article {ART-2007-22,
author = {Sybille Hellebrand and Christian G. Zoellin and Hans-Joachim Wunderlich and Stefan Ludwig and Torsten Coym and Bernd Straube},
title = {{Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)}},
journal = {Informacije MIDEM; Bled, Slovenia},
address = {Ljubljana},
publisher = {MIDEM},
volume = {37(4},
number = {124)},
pages = {212--219},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {2007},
issn = {0352-9045},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {The increased number of fabrication defects, spatial and temporal variability
of parameters, as well as the growing impact of soft errors in nanoelectronic
systems require a paradigm shift in design, verification and test. A robust
design becomes mandatory to ensure dependable systems and acceptable yields.
Design robustness, however, invalidates many traditional approaches for testing
and implies enormous challenges. The RealTest Project addresses these problems
for nanoscale CMOS and targets unified design and test strategies to support
both a robust design and a coordinated quality assurance after manufacturing
and during the lifetime of a system. The paper first gives a short overview of
the research activities within the project and then focuses on a first result
concerning soft errors in combinational logic. It will be shown that common
electrical models for particle strikes in random logic have underestimated the
effects on the system behavior. The refined model developed within the RealTest
Project predicts about twice as many single events upsets (SEUs) caused by
particle strikes as traditional models.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-22&engl=0}
}
@article {ART-2007-12,
author = {Frank Novak and Anton Biasizzo and Yves Bertrand and Marie-Lise Flottes and Luz Balado and Joan Figueras and Stefano di Carlo and Paolo Prinetto and Nicoleta Pricopi and Hans-Joachim Wunderlich and Jean Pierre van der Heyden},
title = {{Academic Network for Microelectronic Test Education}},
journal = {The International Journal of Engineering Education},
publisher = {TEMPUS Publications},
volume = {23},
number = {6},
pages = {1245--1253},
type = {Artikel in Zeitschrift},
month = {November},
year = {2007},
issn = {0949-149X},
isbn = {ijee: 2007/00000023/00000006/art00021},
keywords = {microelectronic circuit test; remote on-line test; digital test; mixed-signal test; memory test, automatic test equipment; test education},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
ee = {http://www.ingentaconnect.com/content/intjee/ijee/2007/00000023/00000006/art00021},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {This paper is an overview of the activities performed in the framework of the
European IST project EuNICE-Test (European Network for Initial and Continuing
Education in VLSI/SOC Testing) using remote automatic test equipment (ATE) ),
addressing the shortage of skills in the microelectronics industry in the field
of electronic testing. The project was based on the experience of the common
test resource centre (CRTC) for French universities. In the framework of the
EuNICE-Test project, the existing network expanded to 4 new academic centres:
Universitat Politecnica de Catalunya, Spain, Politecnico di Torino, Italy,
University of Stuttgart, Germany and Jozef Stefan Institute Ljubljana,
Slovenia. Assessments of the results achieved are presented as well as course
topics and possible future extensions.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-12&engl=0}
}
@article {ART-2007-05,
author = {Valentin Gherman and Hans-Joachim Wunderlich and Juergen Schloeffel and Michael Garbers},
title = {{Deterministic Logic BIST for Transition Fault Testing}},
journal = {IET Computers \& Digital Techniques},
publisher = {Institution of Engineering and Technology},
volume = {1},
number = {3},
pages = {180--186},
type = {Artikel in Zeitschrift},
month = {Mai},
year = {2007},
issn = {1751-8601},
doi = {10.1049/iet-cdt:20060131},
keywords = {Deterministic logic BIST; delay test generation; transition faults},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {BIST is an attractive approach to detect delay faults due to its inherent
support for at-speed test. Deterministic logic BIST (DLBIST) is a technique
which was successfully applied to stuck-at fault testing. As delay faults have
lower random pattern testability than stuck-at faults, the need for DLBIST
schemes is increased. Nevertheless, an extension to delay fault testing is not
trivial, since this necessitates the application of pattern pairs.
Consequently, delay fault testing is expected to require a larger mapping
effort and logic overhead than stuck-at fault testing. In this paper, we
consider the so-called transition fault model, which is widely used for
complexity reasons. We present an extension of a DLBIST scheme for transition
fault testing. Functional justification has been used to generate the required
pattern pairs. The efficiency of the extended scheme is investigated by using
difficult to test industrial designs.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2007-05&engl=0}
}
@article {ART-2006-15,
author = {Yuyi Tang and Hans-Joachim Wunderlich and Piet Engelke and Ilian Polian and Bernd Becker and Juergen Schloeffel and Friedrich Hapke and Michael Wittke},
title = {{X-Masking During Logic BIST and its Impact on Defect Coverage}},
journal = {IEEE Transactions on Very Large Scale Integrated (VLSI) Systems},
publisher = {The Institute of Electrical and Electronics Engineers, Inc.},
volume = {14},
number = {2},
pages = {193--202},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {2006},
issn = {1063-8210},
doi = {10.1109/TVLSI.2005.863742},
keywords = {Defect coverage; logic built-in self test (BIST); resistive bridging faults (RBFs); X-masking},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {We present a technique for making a circuit ready for logic built-in self test
by masking unknown values at its outputs. In order to keep the silicon area
costs low, some known bits in output responses are also allowed to me masked.
These bits are selected based on a stuck-at n-detection based metric, such that
the impact of masking on the defect coverage is minimal. An analysis based on a
probabilistic model for resistive short defects indicates that the coverage
loss for unmodeled defects is negligible for relatively low values of n.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2006-15&engl=0}
}
@article {ART-2006-14,
author = {Bernd Becker and Ilia Polian and Sybille Hellebrand and Bernd Straube and Hans-Joachim Wunderlich},
title = {{DFG-Projekt RealTest - Test und Zuverl{\"a}ssigkeit nanoelektronischer Systeme}},
journal = {it - Information Technology},
publisher = {Oldenbourg Wissenschaftsverlag},
volume = {48},
number = {5},
pages = {304--311},
type = {Artikel in Zeitschrift},
month = {Oktober},
year = {2006},
issn = {1611-2776},
doi = {10.1524/itit.2006.48.5.304},
keywords = {Nanoelektronik; Entwurf; Test; Zuverl{\"a}ssigkeit; Fehlertoleranz/Nano-electronics; Design; Test; Dependability; Fault Tolerance},
language = {Deutsch},
cr-category = {B.7 Integrated Circuits},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Entwurf, Verifikation und Test zuverl{\"a}ssiger nanoelektronischer Systeme
erfordern grundlegend neue Methoden und Ans{\"a}tze. Ein robuster Entwurf wird
unabdingbar um Fertigungsfehler, Parameterschwankungen, zeitabh{\"a}ngige
Materialver{\"a}nderungen und vor{\"u}bergehende St{\"o}rungen zu tolerieren. Gleichzeitig
verlieren gerade dadurch viele traditionelle Testverfahren ihre Aussagekraft.
Im Rahmen des Projekts RealTest werden einheitliche Entwurfs- und
Teststrategien entwickelt, die sowohl einen robusten Entwurf als auch eine
darauf abgestimmte Qualit{\"a}tssicherung unterst{\"u}tzen.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2006-14&engl=0}
}
@article {ART-2002-14,
author = {Rainer Dorsch and Hans-Joachim Wunderlich},
title = {{Reusing Scan Chains for Test Pattern Decompression}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {18},
number = {2},
pages = {231--240},
type = {Artikel in Zeitschrift},
month = {April},
year = {2002},
isbn = {0923-8174},
doi = {10.1023/A:1014968930415},
keywords = {system-on-a-chip; embedded test; BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The paper presents a method for testing a system-on-a-chip by using a
compressed representation of the patterns on an external tester. The patterns
for a certain core under test are decompressed by reusing scan chains of cores
idle during that time. The method only requires a few additional gates in the
wrapper, while the mission logic is untouched. Storage and bandwidth
requirements for the ATE are reduced significantly.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-14&engl=0}
}
@article {ART-2002-11,
author = {Hua-Guo Liang and Sybille Hellebrand and Hans-Joachim Wunderlich},
title = {{Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {18},
number = {2},
pages = {157--168},
type = {Artikel in Zeitschrift},
month = {April},
year = {2002},
issn = {0923-8174},
doi = {10.1023/A:1014993509806},
keywords = {BIST; deterministic BIST; store and generate schemes; test data compression},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a novel architecture for scan-based mixed mode BIST is presented.
To reduce the storage requirements for the deterministic patterns it relies on
a two-dimensional compression scheme, which combines the advantages of known
vertical and hoizontal compression techniques. To reduce both the number of
patterns to be stored and the number of bits to be stored for each pattern,
deterministic test cubes are encoded as seeds of an LFSR (horizontal
compression), and the seeds are again compressed into seeds of a folding
counter sequence (vertical compression). The proposed BIST architecture is
fully compatible with standard scan esign, simple and flexible, so that sharing
between several logic cores is p0ossible. Experimental results show that the
proposed scheme requires less test data storage than previously publiched
approaches providing the same flexibility and scan compatibility.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-11&engl=0}
}
@article {ART-2002-10,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Alexander A. Ivaniuk and Yuri V. Klimets and Vyacheslav N. Yarmolik},
title = {{Efficient On- and Off-Line Testing of Embedded DRAMs}},
journal = {IEEE Transaction on Computers},
publisher = {IEEE Computer Society},
volume = {51},
number = {7},
pages = {801--809},
type = {Artikel in Zeitschrift},
month = {Juli},
year = {2002},
issn = {0018-9340},
doi = {10.1109/TC.2002.1017700},
keywords = {Embedded memories; systems-on-a-chip; online checking; BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {This paper presents an integrated approach for both built-in online and offline
testing of embedded DRAMs. It is based on a new technique for output data
compression which offers the same benefits as signature analysis during offline
test, but also supports efficient online consistency checking. The initial
fault-free memory contents are compressed to a reference characteristic and
compared to test characteristics periodically. The reference characteristic
depends on the memory contents, but unlike similar characteristics based on
signature analysis, it can be easily updated concurrently with WRITE
operations. This way, changes in memory do not require a time consuming
recomputation. The respective test characteristics can be efficiently computed
during the periodic refresh operations of the dynamic RAM. Experiments show
that the proposed technique significantly reduces the time between the
occurrence of an error and its detection (error detection latency). Compared to
error detecting codes (EDC) it also achieves a significantly higher error
coverage at lower hardware costs. Therefore, it perfectly complements standard
online checking approaches relying on EDC, where the concurrent detection of
certain types of errors is guaranteed, but only during READ operations
accessing the erroneous data.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-10&engl=0}
}
@article {ART-2002-09,
author = {Patrick Girard and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel and Hans-Joachim Wunderlich},
title = {{High Defect Coverage with Low Power Test Sequences in a BIST Environment}},
journal = {IEEE Design and Test of Computers},
publisher = {IEEE Computer Society},
volume = {19},
number = {5},
pages = {44--52},
type = {Artikel in Zeitschrift},
month = {September},
year = {2002},
issn = {0740-7475},
doi = {10.1109/MDT.2002.1033791},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A new technique, random single-input change (RSIC) test generation, generates
low-power test patterns that provide a high level of defect coverage during
low-power BIST of digital circuits. The authors propose a parallel BIST
implementation of the RSIC generator and analyze its area-overhead impact.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-09&engl=0}
}
@article {ART-2001-19,
author = {Gundolf Kiefer and Harald Vranken and Erik Jan Marinessen and Hans-Joachim Wunderlich},
title = {{Application of deterministic logic BIST on industrial circuits}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {17},
number = {3},
pages = {351--362},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2001},
isbn = {0923-8174},
doi = {10.1023/A:1012283800306},
keywords = {logic BIST; industrial applications; scan-based BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {We present the application of a deterministic logic BIST scheme based on
bit-flipping on state-of-the-art industrial circuits. Experimental results show
that complete fault coverage can be achieved for industrial circuits up to 100
K gates with 10,000 test patterns, at a total area cost for BIST hardware of
typically 5\% - 15\%. It is demonstrated that a trade-off is possible between
test quality, test time, and silicon area. In contrast to BIST schemes based on
test point insertion no modifications of the circuit under test are required,
complete fault efficiency is guaranteed, and the impact on the design process
is minimized.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2001-19&engl=0}
}
@article {ART-2001-17,
author = {Sybille Hellebrand and Hua-Guo Liang and Hans-Joachim Wunderlich},
title = {{A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {17},
number = {3/4},
pages = {341--349},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2001},
issn = {0923-8174},
doi = {10.1023/A:1012279716236},
keywords = {BIST; deterministic BIST; store and generate schemes},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a
programmable Johnson counter and is called folding counter. Both the
theoretical background and practical algorithms are presented to characterize a
set of deterministic test cubes by a reasonably small number of seeds for a
folding counter. Combined with classical techniques for test width compression
and with pseudo-random pattern generation these new techniques provide an
efficient and flexible solution for scan-based BIST. Experimental results show
that the proposed scheme outperforms previously published approaches based on
the reseeding of LFSRs or Johnson counters.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2001-17&engl=0}
}
@article {ART-2000-18,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Partial Scan}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {16},
number = {3},
pages = {169--177},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2000},
issn = {0923-8174},
doi = {10.1023/A:1008374811502},
keywords = {deterministic scan-based BIST; partial scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An efficient deterministic BIST scheme based on partial scan chains together
with a scan selection algorithm tailored for BIST is presented. The algorithm
determines a minimum number of flipflops to be scannable so that the remaining
circuit has a pipeline-like structure. Experiments show that scanning less
flipflops may even decrease the hardware overhead for the on-chip pattern
generator besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2000-18&engl=0}
}
@article {ART-2000-17,
author = {Stefan Gerstendoerfer and Hans-Joachim Wunderlich},
title = {{Minimized Power Consumption for Scan-Based BIST}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {16},
number = {3},
pages = {203--212},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {2000},
issn = {0923-8174},
doi = {10.1023/A:1008383013319},
keywords = {deterministic scan-based BIST; partial scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Power consumption of digital systems may increase significantly during testing.
In this paper, systems equipped with a scan-based built-in self-test like the
STUMPS architecture are analyzed, the modules and modes with the highest power
consumption are identified, and design modifications to reduce power
consumption are proposed. The design modifications include some gating logic
for masking the scan path activity during shifting, and the synthesis of
additional logic for suppressing random patterns which do not contribute to
increase the fault coverage. These design changes reduce power consumption
during BIST by several orders of magnitude, at very low cost in terms of area
and performance.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2000-17&engl=0}
}
@article {ART-1999-10,
author = {Gundolf Kiefer and Hans-Joachim Wunderlich},
title = {{Deterministic BIST with Multiple Scan Chains}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {14},
number = {1-2},
pages = {85--93},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {1999},
issn = {0923-8174},
doi = {10.1023/A:1008353423305},
keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented.
A procedure is described for synthesizing a pattern generator which stimulates
all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach
while better or even complete fault coverage is obtained at the same time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1999-10&engl=0}
}
@article {ART-1998-15,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Andre Hertwig},
title = {{Mixed-Mode BIST Using Embedded Processors}},
journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
publisher = {Springer Netherlands},
volume = {12},
number = {1-2},
pages = {127--138},
type = {Artikel in Zeitschrift},
month = {Februar},
year = {1998},
issn = {0923-8174},
doi = {10.1023/A:1008294125692},
keywords = {BIST; random pattern testing; deterministic BIST; embedded systems},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {In complex systems, embedded processors may be used to run software for test
pattern generation and response evaluation. For system components which are not
completely random pattern testable, the test programs have to generate
deterministic patterns after random testing. Usually the random test part of
the program requires long run times whereas the part for deterministic testing
has high memory requirements.
In this paper it is shown that an appropriate selection of the random pattern
test method can significantly reduce the memory requirements of the
deterministic part. A new, highly efficient scheme for software-based random
pattern testing is proposed, and it is shown how to extend the scheme for
deterministic test pattern generation. The entire test scheme may also be used
for implementing a scan based BIST in hardware.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-15&engl=0}
}
@article {ART-1998-14,
author = {Albrecht P. Stroele and Hans-Joachim Wunderlich},
title = {{Hardware-Optimal Test Register Insertion}},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
publisher = {IEEE Circuits and Systems Society},
volume = {17},
number = {6},
pages = {531--539},
type = {Artikel in Zeitschrift},
month = {Juni},
year = {1998},
issn = {0278-0070},
doi = {10.1109/43.703833},
keywords = {BILBO; built-in self-test; CBILBO; test register insertion},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {Implementing a built-in self-test by a ``test per clock'' scheme offers
advantages concerning fault coverage, detection of delay faults and test
application time. Such a scheme is implemented by test registers, for instance
BILBOs or CBILBOs, which are inserted into the circuit structure at appropriate
places. An algorithm is presented which is able to find the cost optimal
placement of test registers for nearly all the ISCAS'89 sequential benchmark
circuits, and a suboptimal solution with slightly higher costs is obtained for
all the circuits within a few minutes of computing time. The algorithm can also
be applied to the Minimum Feedback Vertex Set problem in partial scan desing,
and an optimal solution is found for all the benchmark circuits.
The proveably optimal solutions for the benchmark circuits mainly use CBILBOs
which can simultaneously generate test patterns and compact test responses.
Hence, test scheduling is not required, test control is simplified, and test
application time is reduced.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-14&engl=0}
}
@article {ART-1998-13,
author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Andre Hertwig},
title = {{Synthesizing fast, online-testable control units}},
journal = {IEEE Design \& Test of Computers,},
publisher = {IEEE Computer Society},
volume = {15},
number = {4},
pages = {36--41},
type = {Artikel in Zeitschrift},
month = {Oktober},
year = {1998},
issn = {0740-7475},
doi = {10.1109/54.735925},
keywords = {error detection; finite state machines; logic testing},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {The authors present the self-checking bypass pipeline, an online-testable
controller structure for data-dominated applications. For most circuits in a
standard benchmark set, this structure leads to a performance improvement of
more than 30\% with an area overhead less than 15\% that of conventional
online-testable finite-state machines},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-13&engl=0}
}
@article {ART-1998-12,
author = {Hans-Joachim Wunderlich},
title = {{BIST for Systems-on-a-Chip}},
journal = {INTEGRATION, The VLSI Journal},
publisher = {Elsevier Science B.V},
volume = {26},
number = {1-2},
pages = {55--78},
type = {Artikel in Zeitschrift},
month = {Dezember},
year = {1998},
issn = {0167-9260},
doi = {10.1016/S0167-9260(98)00021-2},
keywords = {BIST; Systems-on-chip; Deterministic BIST; Functional BIST},
language = {Englisch},
cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Informatik, Rechnerarchitektur},
abstract = {An increasing part of microelectronic systems is implemented on the basis of
predesigned and preverified modules, so-called cores, which are reused in many
instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many
other functions, and built-in self-test ist the appropriate method for testing
complex systems composed of different cores In this paper, we overview BIST
methods for different types of cores and present advanced BIST solutions.
Special emphasis is put on deterministic BIST methods as they do not require
any modifications of the core under test and help to protect intellectual
property (IP).},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-1998-12&engl=0}
}
@inbook {INBOOK-2009-12,
author = {Christian G. Zoellin and Hans-Joachim Wunderlich},
title = {{Power-Aware Design-for-Test}},
series = {Power-Aware Testing and Test Strategies for Low Power Devices},
publisher = {Springer Berlin Heidelberg},
pages = {117--146},
type = {Beitrag in Buch},
month = {Dezember},
year = {2009},
isbn = {978-1-4419-0927-5},
doi = {10.1007/978-1-4419-0928-2_4},
language = {Englisch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {This chapter describes Design-for-Test (DfT) techniques that allow for
controlling the power consumption and reduce the overall energy consumed during
a test. While some of the techniques described elsewhere in this book may also
involve special DfT, the topics discussed here are orthogonal to those
techniques and may be implemented independently.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-12&engl=0}
}
@inbook {INBOOK-2009-11,
author = {Hans-Joachim Wunderlich and Stefan Holst},
title = {{Generalized Fault Modeling for Logic Diagnosis}},
series = {Models in Hardware Testing},
publisher = {Springer Berlin Heidelberg},
series = {Frontiers in Electronic Testing},
volume = {43},
pages = {133--155},
type = {Beitrag in Buch},
month = {November},
year = {2009},
isbn = {978-90-481-3281-2},
issn = {0929-1296},
doi = {10.1007/978-90-481-3282-9_5},
language = {Englisch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
contact = {Prof. Dr. Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {To cope with the numerous defect mechanisms in nanoelectronic technology, more
and more complex fault models have been introduced. Each model comes with its
own properties and algorithms for test generation and logic diagnosis. In
diagnosis, however, the defect mechanisms of a failing device are not known in
advance, and algorithms that assume a specific fault model may fail. Therefore,
diagnosis techniques have been proposed that relax fault assumptions or even
work without any fault model. In this chapter, we establish a generalized fault
modeling technique and notation. Based on this notation, we describe and
classify existing models and investigate the properties of a fault model
independent diagnosis technique.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-11&engl=0}
}
@inbook {INBOOK-2009-10,
author = {Patrick Girard and Hans-Joachim Wunderlich},
title = {{Models for Power-Aware Testing}},
series = {Models in Hardware Testing},
publisher = {Springer Berlin Heidelberg},
series = {Frontiers in Electronic Testing},
volume = {43},
pages = {187--215},
type = {Beitrag in Buch},
month = {November},
year = {2009},
isbn = {978-90-481-3281-2},
issn = {0929-1296},
doi = {10.1007/978-90-481-3282-9_7},
language = {Englisch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
contact = {Prof. Dr. Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {Power consumption of circuits and systems receives more and more attention. In
test mode, power consumption is even more critical than in system model and has
severe impact on reliability, yield and test costs. This chapter describes the
different types and sources of test power. Power-aware techniques for test
pattern generation, design for test and test data compression are presented
which allow efficient power constrained testing with minimized hardware cost
and test application time.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-10&engl=0}
}
@inbook {INBOOK-2009-09,
author = {Hans-Joachim Wunderlich and Melanie Elm and Michael Kochte},
title = {{Bewertung und Verbesserung der Zuverl{\"a}ssigkeit von mikroelektronischen Komponenten in mechatronischen Systemen}},
series = {Zuverl{\"a}ssigkeit mechatronischer Systeme - Grundlagen und Bewertung in fr{\"u}hen Entwicklungsphasen},
address = {Berlin Heidelberg},
publisher = {Springer Berlin Heidelberg},
series = {VDI-Buch},
pages = {391--464},
type = {Beitrag in Buch},
month = {Februar},
year = {2009},
isbn = {978-3-540-85089-2},
doi = {10.1007/978-3-540-85091-5},
language = {Deutsch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
contact = {Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {In den letzten Jahrzehnten hat der Anteil der informationsverarbeitenden
Komponenten an den Herstellungskosten mechatronischer Systeme rapide
zugenommen. In den 70er Jahren machte die Informationsverarbeitung noch ca. 15\%
des Systems aus. Zu Beginn dieses Jahrtausends sind es bereits {\"u}ber 60\% [8.9],
wie auch aus Abb. 8.1 hervorgeht. Dieser Zuwachs in den Herstellungskosten ist
auf die Zunahme der durch die Informationsverarbeitung realisierten Funktionen
zur{\"u}ckzuf{\"u}hren. Sehr deutlich ist diese Zunahme im Automobil zu beobachten.
W{\"a}hrend das Antiblockiersystem und die digitale Motorsteuerung schon seit
Jahren zum Standard geh{\"o}ren, werden nun zunehmend auch Fahrerassistenz- und
Infotainmentsysteme ins Kraftfahrzeug integriert. Bei diesen Systemen beginnt
die Grenze zwischen klassischer Sicherheits- und Komfortfunktion zu
verschwimmen. Die Bandbreite m{\"o}glichen Fehlverhaltens reicht vom Ausfall des
Navigationssystems {\"u}ber St{\"o}rungen der Zentralverriegelung bis hin zum
automatischen Einleiten von Bremsman{\"o}vern bei hohen Geschwindigkeiten.
Entsprechend ergeben sich hier hohe Anforderungen an die Zuverl{\"a}ssigkeit dieser
Systeme.},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INBOOK-2009-09&engl=0}
}
@book {BOOK-2009-04,
editor = {Bernd Bertsche and Peter G{\"o}hner and Uwe Jensen and Wolfgang Schink{\"o}the and Hans-Joachim Wunderlich},
title = {{Zuverl{\"a}ssigkeit mechatronischer Systeme}},
publisher = {Springer Berlin Heidelberg},
series = {VDI-Buch},
pages = {464},
type = {Buch},
month = {Februar},
year = {2009},
isbn = {978-3-540-85089-2},
doi = {10.1007/978-3-540-85091-5},
language = {Deutsch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=BOOK-2009-04&engl=0}
}
@book {BOOK-2009-03,
editor = {Hans-Joachim Wunderlich},
title = {{Models in Hardware Testing}},
publisher = {Springer Berlin Heidelberg},
series = {Frontiers in Electronic Testing},
volume = {43},
pages = {257},
type = {Buch},
month = {November},
year = {2009},
isbn = {978-90-481-3281-2},
issn = {978-90-481-3281-2},
doi = {10.1007/978-90-481-3282-9},
language = {Englisch},
cr-category = {B.8.2 Performance Analysis and Design Aids},
contact = {Prof. Dr. Hans-Joachim Wunderlich wu@informatik.uni-stuttgart.de},
department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
abstract = {},
url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=BOOK-2009-03&engl=0}
}
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