|Bibliography||Gera, Jurij: Resource Constrained Image Compression for Embedded Systems. |
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Diploma Thesis (2012).
113 pages, english.
|CR-Schema||D.1.3 (Concurrent Programming)|
I.4.2 (Image Processing and Computer Vision Compression (Coding))
I.4.0 (Image Processing and Computer Vision General)
E.4 (Data Coding and Information Theory)
Lossless image compression at high image frame rates requires expensive high-bandwidth data links in embedded systems as lossless compression ratio is typically limited to a factor of 2 or 3. However, we observe that in imaging metrology only object features like edges are considered for further image processing. The image regions containing these features must be detected and transmitted to the decoder with very high quality, i.e. without loss or with only subtle loss. In contrast to that, the remaining background information is considered less important, and can be compressed at a lower bit rate with reduced quality. These circumstances are exploited in this work to achieve higher overall compression ratios and to fit compressed data stream to available bandwidth of the data link, while minimizing the loss of features in important regions. In this thesis first critical requirements are defined, which must be met in order to provide efficient and stable image compression and transmission on standard high bandwidth links of embedded systems. High compression ratio, adaptive image quality, parallelization degree, complexity, memory space requirements and error resilience are some of them. The suitability of the existing methods such as JPEG-LS, JPEG and JPEG2000 will be briefly discussed. As the main task of the thesis, we design an image compression algorithm to fulfil those requirements. The proposed algorithm has been implemented in C# and its properties, such as compression performance and image quality, have been evaluated in simulations using appropriate test image sets. Throughout the work, suitability for hardware implementation is preserved by careful design considerations on the computational and memory space complexity of the proposed algorithm. Because error resilience heavily depends on transmission and storage format, suitable multiplexing and queuing techniques, as well as transmission protocol and data format are considered.
|Department(s)||University of Stuttgart, Institute of Parallel and Distributed Systems, Parallel Systems|
|Superviser(s)||Simon, Prof. Sven; Wang, Zhe|
|Entry date||July 31, 2018|