Masterarbeit MSTR-2018-09

Balakrishnan, Govind: Development of a virtual test bench in a Co-Simulation environment.
Universität Stuttgart, Fakultät Informatik, Elektrotechnik und Informationstechnik, Masterarbeit Nr. 9 (2018).
73 Seiten, englisch.

The embedded system development cycle involves a lot of focus on simulation techniques for verification and validation of the implemented features. Hardware-in-the-loop and software-in-the-loop and Software-in-the-loop techniques are among the most commonly used simulation methodologies in the embedded industry where the embedded system is mostly executed in a simulated environment. But the complexity and cost factors accompanying Hardware-in-the-loop systems as well as the limited real time capabilities of Software-in-the-loop techniques acts as a hindrance in their wide scale adoption. Additionally, with model based development becoming more relevant in embedded system design, there is a further need to effectively couple software models from different vendors with the Hardware-in-the-loop and software-in-the-loop and Software-in-the-loop techniques. Through this thesis, some of the concerns mentioned above are addressed by the establishment of a virtual test bench in a co-simulation environment which supports seamless communication among software models from different sources as well as with the actual Hardware-in-the-loop test setup. Several alternate virtual Hardware-in-the-loop test setups are also explored with the goal of analyzing the behavioral patterns of software models like the virtual Electronic Control Unit model at a much earlier stage of development. The real time performance capabilities of the virtual test bench as well as the virtual Hardware-in-the-loop setups are evaluated and a suitable approach is suggested as a base for the development of future co-simulation test environments. The results of the thesis show that the use of a virtual Hardware-in-the-loop test system based on python and the User Datagram Protocol communication methodology is optimal for real time performance. The virtual Hardware-in-the-loop test system based on Transmission Control Protocol communication methodology also exhibits reasonable performance ratings, and can be used as a reasonable alternative when more end systems are participating in the network in the future. It also highlights the impact of detrimental communication delays being introduced when Simulink models of complex real time systems are used in the co-simulation environment.

Abteilung(en)Universität Stuttgart, Institut für Softwaretechnologie, Software Engineering
BetreuerWagner, Prof. Stefan; Abdulkhaleq, Dr. Asim; Talamas, Brahim
Eingabedatum24. Mai 2019
   Publ. Informatik