|Bibliography||Buntoro, David Prasetyo: Modeling of Design-for-test infrastructure in complex Systems-on-chips. |
University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Master Thesis No. 3304 (2012).
35 pages, english.
|CR-Schema||B.5.1 (Register-Transfer-Level Implementation, Design)|
B.5.3 (Reliability and Testing)
Every integrated circuit contains a piece of design-for-test (DFT) infra- structure in order to guarantee the chip quality after manufacture. The DFT resources are employed only once in the fab and are usually not available during regular system operation.
In order to assess the hardware integrity of a chip over its complete life- cycle, it is promising to reuse the DFT infrastructure as part of system- level test.
In this thesis, the provided system, a Tricore processor from Infineon, must be partitioned and modified in order to enable the autonomous structural test of every component of the system in the field without expensive external tester.
|Full text and|
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|Department(s)||University of Stuttgart, Institute of Technical Computer Science, Computer Architecture|
|Superviser(s)||M.Sc. Alejandro Cook|
|Entry date||September 26, 2012|